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SPEAR1310 Fiches technique(PDF) 46 Page - STMicroelectronics

No de pièce SPEAR1310
Description  Dual-core Cortex A9 embedded MPU for communications
PDF  57 Pages
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Fabricant  STMICROELECTRONICS [STMicroelectronics]
Site Internet  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

SPEAR1310 Fiches technique(HTML) 46 Page - STMicroelectronics

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Security co-processor (C3)
SPEAr1310
46/57
Doc ID 17528 Rev 4
Channel 3: Unified hash with HMAC
ID: 0x00004014
Supported algorithms: HMAC MD5 (hash with 128-bit digest), HMAC SHA1 (hash
with 160-bit digest) and HMAC SHA2 (SHA256 and SHA224 with 256- and 224-bit
digest respectively)
Input FIFO: 16x32 bits
Output FIFO: 8x32 bits
Channel 4: Unified hash 2 with HMAC
ID: 0x00011001
Supported algorithms: HMAC SHA384 (hash with 384-bit digest) and HMAC
SHA512 (hash with 512-bit digest)
Input FIFO: 16x32 bits
Output FIFO: 8x32 bits
Channel 5: Public key accelerator (PKA) v6
ID: 0x00006001
Supported algorithms: modular exponentiation for RSA and Diffie-Hellman (up to
2048 bits), scalar multiplication of elliptic curve points over prime fields for ECC
(up to 384 bits) and Montgomery’s parameter for finite field operations
Input FIFO: 8x32 bits
Output FIFO: 8x32 bits
Channel 6: Random number generator (RNG)
ID: 0x0000F000
Generates a sequence of true random numbers, based on a contiguous analog
oscillator; the sequence has a success ratio of more than 85 % for 20.000 bits,
according to FIPS 140-1 tests
Monitors the entropy of the generated sequence
Input FIFO: 2x32 bits
Output FIFO: 4x32 bits
Channel 7: empty



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