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SPEAR1310 Fiches technique(PDF) 8 Page - STMicroelectronics

No de pièce SPEAR1310
Description  Dual-core Cortex A9 embedded MPU for communications
PDF  57 Pages
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Fabricant  STMICROELECTRONICS [STMicroelectronics]
Site Internet  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

SPEAR1310 Fiches technique(HTML) 8 Page - STMicroelectronics

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Description
SPEAr1310
8/57
Doc ID 17528 Rev 4
Table 1 provides an overview of SPEAr1310 features and capabilities.
Table 1.
SPEAr1310 features and capabilities overview
Category
Feature
Instances / Details
Notes
CPU subsystem
Processor
cores
2x
Cortex A9@600 MHz
32+32 KB L1 per core
Includes:
– 1x 64-bit global timer
– 2x 32-bit timers
– 2x watchdog/timers
L2 Cache
1x
512 KB ECC
Debug & test
2x
JTAG-PTM
Interconnect
Internal bus
1x
64 bit @ 166 MHz
Network-on-chip
Reset and clock
RCG
generator
1x
Reset and clock
generation module
Configuration
MISC
1x
Miscellaneous SoC
configuration registers
Power management PCM
1x
Power control module
Memories
BootROM
1x
32 KB
On-chip ROM for boot
firmware
SRAM
2x
32 KB + 4 KB
Static RAM
MPMC
1x
up to 1 GB
DDR2: 400 MHz + ECC
DDR3: 533 MHz + ECC
DDR 2/3 controller
FSMC
1x
16-/32-bit
Parallel NAND/NOR Flash
Parallel Flash controller
SMI
1x
4x 16 MB C.S.@50Mbps
Serial NOR Flash
SPI Flash controller



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