SPEAR1310 datasheet(21/57 Pages) STMICROELECTRONICS

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SPEAr1310

Giga/Fast Ethernet media access controller (GMAC)

Doc ID 17528 Rev 4

21/57

Giga/Fast Ethernet media access controller (GMAC)

The GMAC IP provides the capability to transmit and receive data over Ethernet.

12.1

Main features

●

Supports 10/100/1000 Mbps data transfer rates with the following PHY interfaces:

–

IEEE 802.3-compliant GMII/MII (default) interface to communicate with an external

Gigabit/Fast Ethernet PHY

–

RGMII (specification version 2.0) interface to communicate with an external gigabit

PHY

–

SGMII (specification version 1.8) interface to communicate with an external gigabit

PHY

Note that the SGMII block inside GMAC comprises the rate adapter layer (RAL)

and the physical coding scheme (PCS) modules: these modules implement a TBI

"like" interface. Outside the chip the SerDes and high-speed I/O modules are

needed to implement the actual SGMII interface.

–

RMII (specification version 1.2 from RMII consortium) interface to communicate

with an external Fast Ethernet PHY (for 10/100 Mbps operations only)

●

Full-duplex operation

–

IEEE 802.3x flow control automatic transmission of zero-quanta pause frame on

flow control input de-assertion

–

Optional forwarding of received pause control frames to the user application

●

Half-duplex operation

–

CSMA/CD Protocol support

–

Flow control using back-pressure support

–

Frame bursting and frame extension in 1000 Mbps half-duplex operation

●

Automatic CRC and pad generation controllable on a per-frame basis

●

Provides options for automatic pad/CRC stripping on receive frames

●

Supports a variety of flexible address filtering modes, such as:

–

Up to 31 48-bit SA address comparison check with masks for each byte

–

64-bit hash filter for multicast and unicast (DA) addresses

–

Option to pass all multicast addressed frames

–

Promiscuous mode support to pass all frames without any filtering for network

monitoring

–

Passes all incoming packets (per filter) with a status report

●

Programmable frame length to support standard or jumbo Ethernet frames with up to

16 KB of size

●

Programmable interframe gap (IFG) (40-96 bit times in steps of 8)

●

Separate 32-bit status for transmit and receive packets

●

IEEE 802.1Q VLAN tag detection for reception frames

●

Self-managed DMA transfers with an internal DMA block

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