SPEAR1310 datasheet(26/57 Pages) STMICROELECTRONICS

26 / 57 page

PCI Express (PCIe)

SPEAr1310

26/57

Doc ID 17528 Rev 4

The features common to both EP and RC mode of the DM cores are:

●

Support for all non-optional features and some optional features defined in the PCI

Express Base 2.0 specification.

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Ultra-low transmit and receive latency

●

Support a max payload size of 256 bytes

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4-KB maximum request size

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Very high accessible bandwidth

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Support for both Gen1 (at 125 MHz) and Gen2 (at 250 MHz) operation

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2.5 Gbps (Gen1) or 5.0 Gbps (gen2) Lane (x1)

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Automatic Lane reversal as specified in the PCI Express 2.0 specification (transmit and

receive)

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Polarity inversion on receive

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Multiple virtual channels (VCs) (maximum of 2)

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Multiple traffic classes (TCs)

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Supports ECRC generation and checking

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Supports PCI Express beacon and wake-up mechanism

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Supports PCI power management

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Supports PCI Express active state power management (ASPM)

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Supports PCI Express advanced error reporting

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Supports Vital product data (VPD)

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Supports PCIe messages for both transmit and receive.

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Supports external priority arbitration (in addition to the internally-implemented transmit

arbitration)

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Supports expansion ROM

Additional features specific to RC mode

The features specific to the RC mode are:

●

Type 1 configuration space

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Application-initiated Lane reversal for situations where the core does not detect Lane 0

(for example, an x4 core connected to an x8 device that has its Lanes reversed)

Additional features specific to EP mode

The features specific to the EP mode are:

●

Alternate routing-ID (ARI)

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Address translation services (ATS)

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Completion timeout ranges

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Function level reset (FLR)

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Type 0 configuration space

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MSI interrupt capability

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