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SPEAR1310 Fiches technique(PDF) 13 Page - STMicroelectronics

No de pièce SPEAR1310
Description  Dual-core Cortex A9 embedded MPU for communications
PDF  57 Pages
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Fabricant  STMICROELECTRONICS [STMicroelectronics]
Site Internet  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

SPEAR1310 Fiches technique(HTML) 13 Page - STMicroelectronics

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SPEAr1310
Clock and reset system
Doc ID 17528 Rev 4
13/57
4
Clock and reset system
This centralized structure provides system synchronization and includes the following
features:
●
Six PLLs. Four of them are fully programmable and offer an EMI reduction mode
(spread spectrum clock generation through dithering) that can replace all traditional
EMI reduction techniques.
–
PLL1 programmable dithered pll, dedicated for Core1 & 2 & AXI/AHB bus &
peripherals. Both core need to run at the same speed
–
PLL2 programmable dithered PLL, dedicated for the 125 MHz clock of the Gigabit
Ethernet MACs
–
PLL3 programmable dithered PLL, for specific embedded IP functions
–
PLL4 programmable dithered PLL, dedicated for the DDR memory controller
(Asynchronous access memory mode)
–
PLL5 low jitter, dedicated for the USB
–
PLL6 for the PCIe controllers
●
Several synthesizers provide different frequencies for different IPs
●
Fully programmable control of clock and reset signals for all slave blocks allowing
sophisticated power management.



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