SPEAR1310 datasheet(6/57 Pages) STMICROELECTRONICS

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Description

SPEAr1310

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Doc ID 17528 Rev 4

Description

The SPEAr1310 is a member of the SPEAr family of embedded MPUs for network devices.

It offers an unprecedented combination of processing performance and aggressive power

reduction control for next-generation communication appliances.

The SPEAr1310 is based on ARM's new multi-core technology (Cortex-A9 SMP/AMP) and it

is manufactured with ST's 55nm HCMOS low power silicon process.

SPEAr1310 targets cost and power sensitive networking applications for the home and

small business as well as telecom infrastructure equipment, with lowest overall leakage

under real operating conditions. The device integrates ARM's latest generation ARMv7 CPU

cores, ST's proven C3 security coprocessor, and advanced connectivity interfaces and

controllers.

Figure 1.

SPEAr1310 system connectivity

The SPEAr1310 internal architecture is based on several shared subsystem logic blocks

that are interconnected through a multilayer interconnection matrix (the BUSMATRIX). The

switch matrix structure allows different subsystem data flows to be executed in parallel

improving the core platform efficiency.

High performance master agents are directly interconnected with the memory controller to

reduce memory access latency. The overall memory bandwidth assigned to each master

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SPEAr1310

DDR2/3 RAM

Parallel

NAND/NOR

Flash

Serial

NOR

Flash

TFT Display

PCIe

Cards /

Modules

USB Peripherals

Mass

Storage

Telecom

Equipment

LCD

KBD

2x I2S

MPMC

FSMC

SMI

3x FE MAC

2x GE MAC

2x USBH

Memory

Card

Power

Supply

2x I2C

3x SATA

MCIF

3x PCIe

PCI

USB OTG

6x UART

EXPI

ADC

GPIO

FPGA

PCI Cards

USB Host or

Peripheral

2x CAN

4x HDLC

(TDM/E1/RS485)

SSP

SPI Peripherals

JTAG

LAN/WAN

Audio I/O

Test &

Debug

FE/GE

PHYs

CAN Network

Audio

Frontend

Keypad

Analog

Sources

Any device

Terminals

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