ADS5294 datasheet(11/67 Pages) TI1

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ADS5294

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SLAS776B – NOVEMBER 2011 – REVISED JULY 2012

Table 1. LVDS Timing at Different Sampling Frequencies - 2 Wire Interface, 7x Serialization (1)

LVDS Output Rate (MSPS)

Setup Time (tsu), ns

Hold Time (tH), ns

tPROG = (6/7) × T + tdelay, ns

(2)

Zero-Crossing of LCLKP to

Data Valid to Zero-

tPROG = delay from Input clock zero-cross

Data Becoming Invalid

Crossing of LCLKP

rising edge to frame clock zero cross (rising

Fs = 1/T

(both edges)

edge)

(both edges)

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

0.34

0.57

0.55

0.8

9.5

0.35

0.64

0.8

1.1

9.5

0.7

0.9

1.2

1.5

9.5

1.3

1.6

1.85

9.5

1.7

2.3

9.5

2.9

3.2

3.5

9.5

6.5

6.7

9.5

(1)

Bit clock and Frame clock jitter has been included in the Setup and hold timing.

(2)

Values below correspond to tdelay, NOT tPROG

Table 2. LVDS Timing at Different Sampling Frequencies - 1 Wire Interface, 14x Serialization (1)

LVDS Output Rate (MSPS)

Setup Time (tsu), ns

Hold Time (tH), ns

tPROG = (5/7) × T + tdelay, ns

(2)

Zero-Crossing of LCLKP to

Data Valid to Zero-

tPROG = delay from Input clock zero-cross

Data Becoming Invalid

Crossing of LCLKP

rising edge to frame clock zero cross (rising

Fs = 1/T

(both edges)

edge)

(both edges)

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

0.28

0.48

0.28

0.6

7.5

10.5

0.5

0.68

0.54

0.8

7.5

10.5

0.62

0.8

1.25

7.5

10.5

1.2

1.4

1.6

1.9

7.5

10.5

3.1

3.3

3.5

7.5

10.5

(1)

Bit clock and Frame clock jitter has been included in the Setup and hold timing.

(2)

Values below correspond to tdelay, NOT tPROG

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