ADS5294 datasheet(45/67 Pages) TI1

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EN_SDR = 1, FALL_SDR = 0

ADCLKp

LCLKp

OUTp

ADCLKp

LCLKp

OUTp

EN_SDR = 1, FALL_SDR = 1

ADS5294

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SLAS776B – NOVEMBER 2011 – REVISED JULY 2012

In addition to programming the phase of the LCLK in the DDR mode, the device can also be made to operate in

SDR mode by setting bit EN_SDR to 1. In the mode, the bit clock (LCLK) is output at 14X times the input clock,

or twice the rate as in DDR mode. Depending on the state of FALL_SDR, the LCLK may be output in either of

the two manners shown in Figure 53. As can be seen in Figure 53, only the LCLK rising (or falling edge) is used

to capture the output data in SDR mode. The SDR mode does not work well beyond 40 MSPS because the

LCLK frequency will become very high.

Figure 53. SDR Interface Modes

OUTPUT DATA RATE CONTROL

ADDR.

D15

D14

D13

D12

D11

D10

(HEX)

DATA_RATE<1> DATA_RATE<0>

In the default mode of operation, the data rate at the output of the ADS5294 is at the sampling rate of the ADC.

This is true even when the custom pattern generator is enabled. In addition, both output data rate and sampling

rate can also be configured to a sub-multiple of the input clock rate.

With the DATA_RATE<1:0> control, the output data rate can be programmed to be a sub-multiple of the ADC

sampling rate. This feature can be used to lower the output data rate, for example when the decimation filter is

used. Without enabling the decimation filter, the sub-multiple ADC sampling rate feature still can be used.

The different settings are listed below:

DATA_RATE<1>

DATA_RATE<0>

Output data rate

Same as ADC sampling rate

1/2 of ADC sampling rate

1/4 of ADC sampling rate

1/8 of ADC sampling rate

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