ADS5294 datasheet(35/67 Pages) TI1

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ADS5294

www.ti.com

SLAS776B – NOVEMBER 2011 – REVISED JULY 2012

DESCRIPTION OF SERIAL REGISTERS

POWER-DOWN MODES

ADDR.

D15

D14

D13

D12

D11

D10

NAME

(HEX)

PDN_CH<8:1>

PDN_PARTIAL

PDN_COMPLETE

PDN_PIN_CFG

Each of the 8 channels can be individually powered down. PDN_CH<N> controls the power-down mode for ADC

channel <N>. In addition to channel-specific power-down, the ADS5294 also has two global power-down modes:

1. The partial power-down mode. It partially powers down the chip; recovery time from the partial power-down

mode is about 10 µs provided that the clock has been running for at least 50 µs before exiting this mode.

2. The complete power-down mode. It completely powers down the chip, and involves a much longer recovery

time 100 µs.

In addition to programming the chip in either of these two power-down modes (through either the PDN_PARTIAL

or PDN_COMPLETE bits), the PD pin itself can be configured as either a partial power-down pin or a complete

power-down pin control. For example, if PDN_PIN_CFG=0 (default), when the PD pin is high, the device enters

complete power-down mode. However, if PDN_PIN_CFG=1, when the PD pin is high, the device enters partial

power-down mode.

LOW FREQUENCY NOISE SUPPRESSION MODE

ADDR.

D15

D14

D13

D12

D11

D10

NAME

(HEX)

LFNS_CH<8:1>

The low frequency noise suppression mode is specifically useful in applications where good noise performance is

desired in the frequency band of 0 to 1 MHz (around DC). Setting this mode shifts the low-frequency noise of the

ADS5294 to approximately Fs/2, thereby, moving the noise floor around DC to a much lower value.

LFNS_CH<8:1> enables this mode individually for each channel. See Figure 38 and Figure 39.

ANALOG INPUT INVERT

ADDR.

D15

D14

D13

D12

D11

D10

NAME

(HEX)

INVERT_CH<8:1>

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