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ADS5294 Fiches technique(PDF) 30 Page - Texas Instruments |
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ADS5294 Fiches technique(HTML) 30 Page - Texas Instruments |
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30 / 67 page ![]() ADS5294 SLAS776B – NOVEMBER 2011 – REVISED JULY 2012 www.ti.com Table 3. Summary of Functions Supported by Serial Interface (1)(2)(3)(4) (continued) ADDR. D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME DESCRIPTION (HEX) 1: Enables a repeating full scale ramp pattern on the outputs; X 0 0 EN_RAMP 0: Normal operation 1:Enables mode wherein output toggles between 2 defined codes; 0 X 0 DUALCUSTOM_PAT 0: Normal operation 1: Enables mode wherein output is a constant specified code; 0 0 X SINGLE_CUSTOM_PAT 0: Normal operation 2 MSBs for single custom pattern (and for the first code of the dual X X BITS_CUSTOM1<13:12> custom patterns) X X BITS_CUSTOM2<13:12> 2 MSBs for second code of the dual custom patterns 1: Software sync bit for test patterns on all 8 CHs; 25 X TP_SOFT_SYNC 0: No sync. Note: in order to synchronize the digital filters using the SYNC pin, this bit must be set as 0. 1: PRBS test pattern enable bit; X PRBS_TP_EN 0: PRBS test pattern disabled X PRBS_MODE_2 PRBS 9 bit LFSR (23bit LFSR is default) 1: Enable PRBS seed to be chosen from register 0x23 and 0x24; X PRBS_SEED_FROM_REG 0: Disabled 1: Enable the external SYNC feature for syncing test patterns. X TP_HARD_SYNC 0: Inactive. Note: in order to synchronize the digital filters using the SYNC pin, this bit must be set as 0. 12 lower bits for single custom pattern (and for the first code of the 26 X X X X X X X X X X X X BITS_CUSTOM1<11:0> dual custom pattern). 27 X X X X X X X X X X X X BITS_CUSTOM2<11:0> 12 lower bits for second code of the dual custom pattern Enables the bit order output. X EN_BITORDER 0 = Byte wise, 1 = Word wise Selects between bytewise and bit wise 1: bit-wise, odd bits come out on one wire and even bits come out on 0 X BIT_WISE other wire 0: byte-wise, upper bits on one wire and lower bits on other wire 28 Note: D15 must be set to '0' for this mode 1: Output format is one sample on one LVDS wire and next sample on other LVDS wire. 1 X X X X X X X X EN_WORDWISE__BY_CH<7:0> 0: Data comes out in two-wire mode with upper set of bits on one channel and lower set of bits on the other. Note: D15 must set '1' for this mode. 1: Enables filter blocks - global control; X GLOBAL_EN_FILTER 0: Inactive 29 1: Enables channel averaging mode; X EN_CHANNEL_AVG 0: Inactive X X X X GAIN_CH1<3:0> Programmable gain - Channel 1 X X X X GAIN_CH2<3:0> Programmable gain - Channel 2 2A X X X X GAIN_CH3<3:0> Programmable gain - Channel 3 X X X X GAIN_CH4<3:0> Programmable gain - Channel 4 30 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s) :ADS5294 |
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