ADS5294 datasheet(44/67 Pages) TI1

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ADCLKp

LCLKp

OUTp

ADCLKp

LCLKp

OUTp

PHASE_DDR<1:0> = 00

ADCLKp

LCLKp

OUTp

PHASE_DDR<1:0> = 10

ADCLKp

LCLKp

OUTp

PHASE_DDR<1:0> = 01

PHASE_DDR<1:0> = 11

ADCLKp

LCLKp

OUTp

PHASE_DDR<1:0> = 10

ADS5294

SLAS776B – NOVEMBER 2011 – REVISED JULY 2012

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Where k is set as described by the HPF_corner registers (one for each channel). Also the HPF_EN bit in each

BIT CLOCK PROGRAMMABILITY

ADDR.

D15

D14

D13

D12

D11

D10

NAME

(HEX)

PHASE_DDR<1:0>

EN_SDR

FALL_SDR

The output interface of the ADS5294 is normally a DDR interface, with the LCLK rising edge and falling edge

transitions in the middle of alternate data windows. This default phase is shown in Figure 51.

Figure 51. Default Phase of LCLK

The phase of LCLK can be programmed relative to the output frame clock and data using bits

PHASE_DDR<1:0>. The LCLK phase modes are shown in Figure 52.

Figure 52. Phase Programmability Modes for LCLK

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