ST10F280_12 datasheet(50/239 Pages) STMICROELECTRONICS

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Internal Flash memory

ST10F280

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Doc ID 8673 Rev. 3

of the loaded code or data. It may also contain a code sequence to change the system

configuration and enable the bus interface to store the received data into external memory.

This process may go through several iterations or may directly execute the final application.

In all cases the ST10F280 will still run in BSL mode, that means with the watchdog timer

disabled and limited access to the internal Flash area.

All code fetches from the internal Flash area (00’0000h...00’7FFFh or 01’0000h...01’7FFFh,

if mapped to segment 1) are redirected to the special Boot-ROM. Data fetches access will

access the internal Boot-ROM of the ST10F280, if any is available, but will return undefined

data on ROMless devices.

5.6.4

Exiting bootstrap loader mode

In order to execute a program in normal mode, the BSL mode must be terminated first. The

ST10F280 exits BSL mode upon a software reset (ignores the level on P0L.4) or a hardware

reset (P0L.4 must be high). After a reset the ST10F280 will start executing from location

00’0000h of the internal Flash or the external memory, as programmed via pin EA.

5.6.5

Choosing the baud rate for the BSL

The calculation of the serial Baud rate for ASC0 from the length of the first zero Byte that is

received, allows the operation of the bootstrap loader of the ST10F280 with a wide range of

Baud rates. However, the upper and lower limits have to be kept, in order to insure proper

data transfer.

The ST10F280 uses timer T6 to measure the length of the initial zero Byte. The quantization

uncertainty of this measurement implies the first deviation from the real Baud rate, the next

deviation is implied by the computation of the S0BRL reload value from the timer contents.

The formula below shows the association:

For a correct data transfer from the host to the ST10F280 the maximum deviation between

the internal initialized Baud rate for ASC0 and the real Baud rate of the host should be below

2.5%. The deviation (FB, in percent) between host Baud rate and ST10F280 Baud rate can

be calculated via the formula below:

Note:

Function (FB) does not consider the tolerances of oscillators and other devices supporting

the serial communication.

This Baud rate deviation is a nonlinear function depending on the CPU clock and the Baud

rate of the host. The maxima of the function (FB) increase with the host Baud rate due to the

ST10F280

CPU

S0BRL

()

------------------------------------------------

S0BR L

–

--------------------

---

CPU

Host

-----------------

Con tr

Host

–

Con tr

--------------------------------------------

100

% ,

2.5

≤

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