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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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ST10F280 Fiches technique(PDF) 63 Page - STMicroelectronics |
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ST10F280 Fiches technique(HTML) 63 Page - STMicroelectronics |
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63 / 239 page  ST10F280 External bus controller Doc ID 8673 Rev. 3 63/239 7.1 Programmable chip select timing control The ST10F280 allows the user to adjust the position of the CSx lines changes. By default (after reset), the CSx lines are changing half a CPU clock cycle (12.5 ns at fCPU = 40MHz) after the rising edge of ALE. With the CSCFG bit set in the SYSCON register, the CSx lines are changing with the rising edge of ALE, thus the CSx lines are changing at the same time the address lines are changing. See Section 19.2: System configuration registers for detailed description of SYSCON register. Figure 11. Chip select delay 7.2 READY programmable polarity The active level of the READY pin can be selected by software via the RDYPOL bit in the BUSCONx registers. When the READY function is enabled for a specific address window, |
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