ST10F280_12 datasheet(35/239 Pages) STMICROELECTRONICS

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ST10F280

Internal Flash memory

Doc ID 8673 Rev. 3

35/239

5.3.3

Flash Status Register

The Flash Status register is used to flag the status of the Flash memory and the result of an

operation. This register can be accessed by Read cycles during the program-Erase

Controller operations. The program or erase operation can be controlled by data polling on

bit FSB.7 of Status Register, detection of Toggle on FSB.6 and FSB.2, or Error on FSB.5

and Erase Timeout on FSB.3 bit. Any read attempt in Flash during EPC operation will

automatically output these five bits. The EPC sets bit FSB.2, FSB.3, FSB.5, FSB.6 and

FSB.7. Other bit are reserved for future use and should be masked.

Flash Status

Address:

See note for address

Type:

---

FSB.7 FSB.6 FSB.5

FSB.3 FSB.2

FSB.7 Flash Status bit 7: Data Polling Bit

Programming Operation: this bit outputs the complement of the bit 7 of the word being

programmed, and after completion, will output the bit 7 of the word programmed.

Erasing Operation: outputs a ‘0’ during erasing, and ‘1’ after erasing completion.

If the block selected for erasure is (are) protected, FSB.7 will be set to ‘0’ for about 100 µs,

and then return to the previous addressed memory data value.

FSB.7 will also flag the Erase Suspend Mode by switching from ‘0’ to ‘1’ at the start of the

Erase Suspend.

During Program operation in Erase Suspend Mode, FSB.7 will have the same behaviour as

in normal Program execution outside the Suspend mode.

FSB.6 Flash Status bit 6: Toggle Bit

Programming or Erasing Operations: successive read operations of Flash Status register will

deliver complementary values. FSB.6 will toggle each time the Flash Status register is read.

The Program operation is completed when two successive reads yield the same value. The

next read will output the bit last programmed, or a ‘1’ after Erase operation

FSB.6 will be set to‘1’ if a read operation is attempted on an Erase Suspended block. In

addition, an Erase Suspend/Resume command will cause FSB.6 to toggle.

FSB.5 Flash Status bit 5: Error Bit

This bit is set to ‘1’ when there is a failure of Program, block or chip erase operations.This bit

will also be set if a user tries to program a bit to ‘1’ to a Flash location that is currently

programmed with ‘0’.

The error bit resets after Read/Reset instruction.

In case of success, the Error bit will be set to ‘0’ during Program or Erase and then will

output the bit last programmed or a ‘1’ after erasing

FSB.3 Flash Status bit 3: Erase Time-out Bit

This bit is cleared by the EPC when the last Block Erase command has been entered to the

Command Interface and it is awaiting the Erase start. When the time-out period is finished,

after 96 µs, FSB.3 returns back to ‘1’.

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