ST10F280_12 datasheet(24/239 Pages) STMICROELECTRONICS

24 / 239 page

Ball data

ST10F280

24/239

Doc ID 8673 Rev. 3

NMI

Non-Maskable Interrupt Input. A high to low transition at this pin

causes the CPU to vector to the NMI trap routine. If bit PWDCFG =

‘0’ in SYSCON register, when the PWRDN (power down)

instruction is executed, the NMI pin must be low in order to force

the ST10F280 to go into power down mode. If NMI is high and

PWDCFG =’0’, when PWRDN is executed, the part will continue to

run in normal mode.

If not used, pin NMI should be pulled high externally.

XPWM.0

XPWM Channel 0 Output

XPWM.1

XPWM Channel 1 Output

XPWM.2

XPWM Channel 2 Output

XPWM.3

XPWM Channel 3 Output

XADCINJ

Output trigger for ADC channel injection

VAREF

Reference voltage for the A/D converter.

VAGND

Reference ground for the A/D converter.

RPD

M17

I/O

Timing pin for the return from powerdown circuit and

synchronous/asynchronous reset selection.

DC1

3.3V Decoupling pin: a decoupling capacitor of ~330 nF must be

connected between this pin and nearest VSS pin.

DC2

U11

3.3V Decoupling pin: a decoupling capacitor of ~330 nF must be

connected between this pin and VSS nearest pin.

VDD

A12

A14

U15

P17

L17

G17

Digital Supply Voltage: + 5 V during normal operation, idle mode

and power down mode

Table 1.

Ball description (continued)

Symbol

Ball

number

Type

Function

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