ST10F280_12 datasheet(37/239 Pages) STMICROELECTRONICS

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ST10F280

Internal Flash memory

Doc ID 8673 Rev. 3

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data xx54h at address 2AA8h). Any successive read cycle following a Read/Reset

instruction will read the memory array. A Wait cycle of 10µs is necessary after a Read/Reset

command if the memory was in program or Erase mode.

Program Word (PW). This instruction uses four write cycles. After the two Cl enable coded

cycles, the Program Word command xxA0h is written at address 1554h. The following write

cycle will latch the address and data of the word to be programmed. Memory programming

can be done only by writing 0's instead of 1's, otherwise an error occurs. During

programming, the Flash Status is checked by reading the Flash Status bit FSB.2, FSB.5,

FSB.6 and FSB.7 which show the status of the EPC. FSB.2, FSB.6 and FSB.7 determine if

programming is on going or has completed, and FSB.5 allows a check to be made for any

possible error.

Block Erase (BE). This instruction uses a minimum of six command cycles. The erase

enable command xx80h is written at address 1554h after the two-cycle CI enable sequence.

The erase confirm code xx30h must be written at an address related to the block to be

erased preceded by the execution of a second CI enable sequence. Additional erase

confirm codes must be given to erase more than one block in parallel. Additional erase

confirm commands must be written within a defined time-out period. The input of a new

Block Erase command will restart the time-out period.

When this time-out period has elapsed, the erase starts. The status of the internal timer can

be monitored through the level of FSB.3, if FSB.3 is ‘0’, the Block Erase command has been

given and the timeout is running; if FSB.3 is ‘1’, the timeout has expired and the EPC is

erasing the block(s).

If the second command given is not an erase confirm or if the coded cycles are wrong, the

instruction aborts, and the device is reset to Read Mode. It is not necessary to program the

block with 0000h as the EPC will do this automatically before the erasing to FFFFh. Read

operations after the EPC has started, output the Flash Status Register. During the execution

of the erase by the EPC, the device accepts only the Erase Suspend and Read/Reset

instructions. Data Polling bit FSB.7 returns ‘0’ while the erasure is in progress, and ‘1’ when

it has completed. The Toggle bit FSB.2 and FSB.6 toggle during the erase operation. They

stop when erase is completed. After completion, the Error bit FSB.5 returns ‘1’ if there has

been an erase failure because erasure has not completed even after the maximum number

of erase cycles have been executed by the EPC, in this case, it will be necessary to input a

Read/Reset to the Command Interface in order to reset the EPC.

Chip Erase (CE). This instruction uses six write cycles. The Erase Enable command xx80h,

must be written at address 1554h after CI-Enable cycles. The Chip Erase command xx10h

must be given on the sixth cycle after a second CI-Enable sequence. An error in command

sequence will reset the CI to Read mode. It is NOT necessary to program the block with

0000h as the EPC will do this automatically before the erasing to FFFFh. Read operations

after the EPC has started output the Flash Status Register. During the execution of the

erase by the EPC, Data Polling bit FSB.7 returns ‘0’ while the erasure is in progress, and ‘1’

when it has completed. The FSB.2 and FSB.6 bit toggle during the erase operation. They

stop when erase is finished. The FSB.5 error bit returns "1" in case of failure of the erase

operation. The error flag is set after the maximum number of erase cycles have been

executed by the EPC. In this case, it will be necessary to input a Read/Reset to the

Command Interface in order to reset the EPC.

Erase Suspend (ES). This instruction can be used to suspend a Block Erase operation by

giving the command xxB0h without any specific address. No CI-Enable cycles is required.

Erase Suspend operation allows reading of data from another block and/or the programming

in another block while erase is in progress. If this command is given during the time-out

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