ST10F280_12 datasheet(40/239 Pages) STMICROELECTRONICS

40 / 239 page

Internal Flash memory

ST10F280

40/239

Doc ID 8673 Rev. 3

●

Generally, command sequences cannot be written to Flash by instructions fetched from

the Flash itself. Thus, the Flash commands must be written by instructions, executed

from internal RAM or external memory.

●

Command cycles on the CPU interface need not to be consecutively received (pauses

allowed). The CPU interface delivers dummy read data for not used cycles within

command sequences.

●

All addresses of command cycles shall be defined only with Register-indirect

addressing mode in the according move instructions. Direct addressing is not allowed

for command sequences. Address segment or data page pointer are taken into account

for the command address value.

Erase Resume

Addr.(1)

X(2)

Read Data Polling or Toggle bit until Erase completes or

Erase is suspended another time.

Data

xx30h

Set Block/Code

Protection

Addr.(1)

x2A54h

x15A8h

x2A54h

Any odd

word

address(7)

Data

xxA8h

xx54h

xxC0h

WPR(8)

Read Protection

Status

Addr.(1)

x2A54h

x15A8h

x2A54h

Any odd

word

address(7)

Read Protection Register

until a new write cycle is

initiated.

Data

xxA8h

xx54h

xx90h

Read

Block

Temporary

Unprotection

BTU

Addr.(1)

x2A54h

x15A8h

x2A54h

X(2)

Data

xxA8h

xx54h

xxC1h

xxF0h

Code

Temporary

Unprotection

CTU

Addr.(1)

MEM(9)

Write cycles must be executed from Flash.

Data

FFFFh

Code

Temporary

Protection

CTP

Addr.(1)

MEM(9)

Write cycles must be executed from Flash.

Data

FFFBh

Address bit A14, A15 and above are don’t care for coded address inputs.

X = do not care.

WA = Write Address: address of memory location to be programmed.

WD = Write Data: 16-bit data to be programmed.

Optional, additional blocks addresses must be entered within a time-out delay (96 µs) after last write entry, timeout status

can be verified through FSB.3 value. When full command is entered, read Data Polling or Toggle bit until Erase is

completed or suspended

Read Data Polling or Toggle bit until Erase completes.

Odd word address = 4n-2 where n = 0, 1, 2, 3..., ex. 0002h, 0006h...

WPR = Write protection register. To protect code, bit 15 of WPR must be ‘0’. To protect block N (N=0,1,...), bit N of WPR

must be ‘0’. Bit that are already at ‘0’ in protection register must also be ‘0’ in WPR, else a writing error will occurs (it is not

possible to write a ‘1’ in a bit already programmed at ‘0’).

MEM = any address inside the Flash memory space. Absolute addressing mode must be used (MOV MEM, Rn), and

instruction must be executed from Flash memory space.

Table 3.

Instructions (continued)

Instruction

Mne Cycle

1st

Cycle

2nd

Cycle

3rd

Cycle

4th

Cycle

5th

Cycle

6th

Cycle

7th

Cycle

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