ST10F280_12 datasheet(48/239 Pages) STMICROELECTRONICS

48 / 239 page

Internal Flash memory

ST10F280

48/239

Doc ID 8673 Rev. 3

When the ST10F280 has entered BSL mode, the following configuration is automatically set

(values that deviate from the normal reset values, are marked):

In this case, the watchdog timer is disabled, so the bootstrap loading sequence is not time

limited.

Pin TXD0 is configured as output, so the ST10F280 can return the identification Byte.

Even if the internal Flash is enabled, no code can be executed out of it.

The hardware that activates the BSL during reset may be a simple pull-down resistor on

P0L.4 for systems that use this feature upon every hardware reset.

A switchable solution (via jumper or an external signal) can be used for systems that

only temporarily use the bootstrap loader (see Figure 6).

After sending the identification Byte the ASC0 receiver is enabled and is ready to

receive the initial 32 Bytes from the host. A half duplex connection is therefore sufficient to

feed the BSL.

5.6.2

Memory configuration after reset

The configuration (and the accessibility) of the ST10F280’s memory areas after reset in

Bootstrap-Loader mode differs from the standard case. Pin EA is not evaluated when BSL

mode is selected, and accesses to the internal Flash area are partly redirected, while the

ST10F280 is in BSL mode (see Figure 7). All code fetches are made from the special Boot-

ROM, while data accesses read from the internal user Flash. Data accesses will return

undefined values on ROMless devices.

The code in the Boot-ROM is not an invariant feature of the ST10F280. User software

should not try to execute code from the internal Flash area while the BSL mode is still active,

as these fetches will be redirected to the Boot-ROM. The Boot-ROM will also “move” to

segment 1, when the internal Flash area is mapped to segment 1 (see Figure 7).

Watchdog Timer:

Disabled

0E00h

Context Pointer CP:

FA00h

FA40h

Stack Pointer SP:

FA40h

FA0Ch 0<->C

8011h

acc. to startup

configuration

Acc. to ‘00’ Byte

P3.10 / TXD0:

‘1’

DP3.10:

‘1’

ST10F280 Fiches technique(PDF) 48 Page - STMicroelectronics

ST10F280 Fiches technique(HTML) 48 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Fiches technique Télécharger

Lien URL