ST10F280_12 datasheet(34/239 Pages) STMICROELECTRONICS

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Internal Flash memory

ST10F280

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Doc ID 8673 Rev. 3

5.2.8

Power supply, reset

The Flash module uses a single power supply for both read and write functions. Internally

generated and regulated voltages are provided for the program and erase operations from

5V supply. Once a program or erase cycle has been completed, the device resets to the

standard read mode. At power-on, the Flash memory has a setup phase of some

microseconds (dependent on the power supply ramp-up). During this phase, Flash can not

be read. Thus, if EA pin is high (execution will start from Flash memory), the CPU remains in

reset state until the Flash can be accessed.

5.3

Architectural description

The Flash module distinguishes two basic operating modes, the standard read mode and

the command mode. The initial state after power-on and after reset is the standard read

mode.

5.3.1

Read mode

The Flash module enters the standard operating mode, the read mode:

●

After reset command

●

After every completed erase operation

●

After every completed programming operation

●

After every other completed command execution

●

Few microseconds after a CPU-reset has started

●

After incorrect address and data values of command sequences or writing them in an

improper sequence

●

After incorrect write access to a read protected Flash memory

The read mode remains active until the last command of a command sequence is decoded

which starts directly a Flash array operation, such as:

●

Erase one or several blocks

●

Program a word into Flash array

●

Protect / temporary unprotect a block.

In the standard read mode read accesses are directly controlled by the Flash memory array,

delivering a 32-bit double Word from the addressed position. Read accesses are always

aligned to double Word boundaries. Thus, both low order address bit A1 and A0 are not

used in the Flash array for read accesses. The high order address bit A18/A17/A16 define

the physical 64K Bytes segment being accessed within the Flash array.

5.3.2

Command mode

Every operation besides standard read operations is initiated by commands written to the

Flash command register. The addresses used for command cycles define in conjunction

with the actual state the specific step within command sequences. With the last command of

a command sequence, the Erase-Program Controller (EPC) starts the execution of the

command. The EPC status is indicated during command execution by:

●

Status Register

●

Ready/Busy signal

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