ST10F280_12 datasheet(41/239 Pages) STMICROELECTRONICS

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ST10F280

Internal Flash memory

Doc ID 8673 Rev. 3

41/239

5.3.6

Reset processing and initial State

The Flash module distinguishes two kinds of CPU reset types

The lengthening of CPU reset:

●

Is not reported to external devices by bidirectional pin

●

Is not enabled in case of external start of CPU after reset.

5.4

Flash memory configuration

The default memory configuration of the ST10F280 Memory is determined by the state of

the EA pin at reset. This value is stored in the Internal ROM Enable bit (named ROMEN) of

the SYSCON register.

When ROMEN = 0, the internal Flash is disabled and external ROM is used for startup

control. Flash memory can later be enabled by setting the ROMEN bit of SYSCON to 1. The

code performing this setting must not run from a segment of the external ROM to be

replaced by a segment of the Flash memory, otherwise unexpected behaviour may occur.

For example, if external ROM code is located in the first 32K Bytes of segment 0, the first

32K Bytes of the Flash must then be enabled in segment 1. This is done by setting the

ROMS1 bit of SYSCON to 0 before or simultaneously with setting of ROMEN bit. This must

be done in the externally supplied program before the execution of the EINIT instruction.

If program execution starts from external memory, but access to the Flash memory mapped

in segment 0 is later required, then the code that performs the setting of ROMEN bit must be

executed either in the segment 0 but above address 00’8000h, or from the internal RAM.

Bit ROMS1 only affects the mapping of the first 32K Bytes of the Flash memory. All other

parts of the Flash memory (addresses 01’8000h 08’FFFFh) remain unaffected.

The SGTDIS Segmentation Disable / Enable must also be set to 0 to allow the use of the full

512K Bytes of on-chip memory in addition to the external boot memory. The correct

procedure on changing the segmentation registers must also be observed to prevent an

unwanted trap condition:

●

Instructions that configure the internal memory must only be executed from external

memory or from the internal RAM.

●

An Absolute Inter-Segment Jump (JMPS) instruction must be executed after Flash

enabling, to the next instruction, even if this next instruction is located in the

consecutive address.

●

Whenever the internal Memory is disabled, enabled or remapped, the DPPs must be

explicitly (re)loaded to enable correct data accesses to the internal memory and/or

external memory.

5.5

Application examples

5.5.1

Handling of Flash addresses

All command, Block, Data and register addresses to the Flash have to be located within the

active Flash memory space. The active space is that address range to which the physical

Flash addresses are mapped as defined by the user. When using data page pointer (DPP)

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