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PM0214

The STM32 Cortex-M4 instruction set

244

3.6.1

MUL, MLA, and MLS

Multiply, multiply with accumulate, and multiply with subtract, using 32-bit operands, and

producing a 32-bit result.

Syntax

MUL{S}{cond} {Rd,} Rn, Rm ; Multiply

MLA{cond} Rd, Rn, Rm, Ra ; Multiply with accumulate

MLS{cond} Rd, Rn, Rm, Ra ; Multiply with subtract

where:

•

‘cond’ is an optional condition code (see Conditional execution on page 64)

•

‘S’ is an optional suffix. If S is specified, the condition code flags are updated on the

result of the operation (see Conditional execution on page 64).

•

‘Rd’ is the destination register. If Rd is omitted, the destination register is Rn

•

‘Rn’, ‘Rm’ are registers holding the values to be multiplied

•

‘Ra’ is a register holding the value to be added to or subtracted from

Operation

The MUL instruction multiplies the values from Rn and Rm, and places the least significant 32

bits of the result in Rd.

The MLA instruction multiplies the values from Rn and Rm, adds the value from Ra, and

places the least significant 32 bits of the result in Rd.

The MLS instruction multiplies the values from Rn and Rm, subtracts the product from the

value from Ra, and places the least significant 32 bits of the result in Rd.

The results do not depend on whether the operands are signed or unsigned.

Restrictions

In these instructions, do not use SP and do not use PC.

If you use the S suffix with the MUL instruction:

•

Rd, Rn, and Rm must all be in the range R0 to R7

•

Rd must be the same as Rm

•

You must not use the cond suffix

Condition flags

If S is specified, the MUL instruction:

•

Updates the N and Z flags according to the result

•

Does not affect the C and V flags

Examples

MUL R10, R2, R5

; multiply, R10 = R2 x R5

MLA R10, R2, R1, R5

; multiply with accumulate, R10 = (R2 x R1) + R5

MULS R0, R2, R2

; multiply with flag update, R0 = R2 x R2

MULLT R2, R3, R2

; conditionally multiply, R2 = R3 x R2

MLS R4, R5, R6, R7

; multiply with subtract, R4 = R7 - (R5 x R6)

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