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STLC5465B Fiches technique(PDF) 55 Page - STMicroelectronics

No de pièce STLC5465B
Description  MULTI-HDLCWITH n x 64 SWITCHING MATRIX ASSOCIATED
PDF  101 Pages
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Fabricant  STMICROELECTRONICS [STMicroelectronics]
Site Internet  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STLC5465B Fiches technique(HTML) 55 Page - STMicroelectronics

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NCS0/1
NDSACK 0/
DTAC K /
NREADY
NAS/
ALE
ND S/
NRD
D0/15
R/W /
NWR
A0/15 / AD0/15
A16/23 NBHE
t3
t2
t1
t4
t7
t8
t9
t12
t10
Figure 44 : ST10 (C16x) Read Cycle; Multiplexed A/D
VII - MICROPROCESSOR TIMING (continued)
VII.2 - ST10/C16x mult. A/D, MOD0 = 1, MOD1 = 0, MOD2 = 1
Symbol
Parameter
Min.
Typ.
Max.
Unit
t1
Delay Not Ready/NRD (if NCS0/1 = 0), (30pF)
Delay when immediate access
VDD =5V
V DD = 3.3V
0
98
108
ns
ns
ns
t2
Hold Time Chip Select / NRD
10
ns
t3
Delay Not Ready / NRD rising edge
Delay when immediate access
VDD =5V
V DD = 3.3V
0
98
108
ns
ns
ns
t4
Width ALE
20
ns
t5
Set-up Time Address / ALE
5
ns
t6
Hold Time Address /ALE
V DD =5V
V DD = 3.3V
5
10
ns
ns
t7
Data valid after ready
0
15
ns
t8
Data bus at high impedance after NRD (30pF)
0
15
ns
t9
Set-up Time NBHE, Address A 16/23/ALE
5
ns
t10
Hold Time NBHE / NRD
10
ns
t12
Delay NRD / NCS
0
ns
STLC5465B
55/101



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