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STLC5465B Fiches technique(PDF) 16 Page - STMicroelectronics |
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STLC5465B Fiches technique(HTML) 16 Page - STMicroelectronics |
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16 / 101 page ![]() From SMCR Register CM (when Read) LOOP DATA MEMORIES 64kb/s and n x 64kb/s CONNECTION MEMORY Sequence Integrity, LOOP, PRSA, PRSG, INS, OTSV Tx HDLC Rx GCI S/ P IMTD Sequence Integrity INS 1 1 A 1 CM 1 PRSG PSEUDO RANDOM SEQUENCE GENERATOR 211 -1 Rec. O.152 PRSG SGV PSEUDO RANDOM SEQUENCE ANALYZER 211 -1 Rec. O.152 PRSA SAV GCIR BIT SYNCHRO Tx GCI ME P/ S Rx HDLC D4/5 D7 D0/7 1 1 D D D D A 1 CMDR Data Register CMAR Address Register SFCR R Sequence Fault Counter Register HDLCM 1 D7 D D I I N N ’ 0/ 7 7 D4/5 BIT SYNCHRO DIN 0/7 DOUT 0/7 Internal Bus From OMCR Register OMV (per multiplex) From Connection Memory OTSV (per channel) From N DIS PIN (for all multiplexes) PRSG : Pseudo Random Sequence Generator PRSA : Pseudo Random Sequence Analyzer OTSV : Output Time Slot Validated INS : Insert ME : g Messa e Enable IMTD : Increased Min Throughtput Delay SGV : Sequence Generator Validated SAV : Sequence Analyzer Validated CM : Connection Memory (from CMAR Register) OR Figure 2 : Switching Matrix Data Path III - FUNCTIONAL DESCRIPTION (continued) STLC5465B 16/101 |
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