STLC5465B datasheet(91/101 Pages) STMICROELECTRONICS

91 / 101 page

TBFS

: Time Base running with Frame Synchronisation signal

TBFS=1, the Time Base defined by the Timer Register (see page 92) is running on the rising

edge of Frame Synchronisation signal.

TBFS=0, the Time Base defined by the Timer Register is running on the rising edge of MCLK

signal.

VIII.29 - Interrupt Register - IR (38)H

bit15

bit8

bit7

bit 0

SFCO PRSR

TIM

INT

FOV

INT

FWAR

FOV

FWAR

FOV

FWAR

ICOV

MTX MRX C/IRX HDLC

After reset (0000)H

This register is read only.

When this register is read by the microprocessor, this register is reset (0000)H.

If not masked, each bit at ”1” generates ”1” on INT0 pin.

HDLC

: HDLC INTERRUPT

HDLC = 1, Tx HDLC or Rx HDLC has generated an interrupt The status is in the HDLC

queue.

C/IRX

: Command/Indicate Rx Interrupt

C/IRX = 1, Rx Commande/Indicate has generated an interrupt. The status is in the HDLC

queue.

MRX

: Rx MONITOR CHANNEL INTERRUPT

MRX = 1, one Rx MONITOR CHANNEL has generated an interrupt.The status is in the Rx

Monitor Channel queue.

MTX

: Tx MONITOR CHANNEL INTERRUPT

MTX = 1, one or several Tx MONITOR CHANNELS have generated an interrupt. Transmit

Monitor Interrupt Register (TMIR) indicates the Tx Monitor Channels which have generated

this interrupt.

ICOV

: INTERRUPT CIRCULAR OVERLOAD

ICOV = 1, One of three circular interrupt memories is completed.

RxFWAR

: Rx DMA CONTROLLER FIFO WARNING

RxFWAR = 1, Rx DMA CONTROLLER has generated an interrupt, its fifo is 3/4 completed.

RxFOV

: Rx DMA CONTROLLER FIFO OVERLOAD

RxFOV = 1, Rx DMA CONTROLLER has generatedan interrupt, it cannot transfer data from

Rx HDLC to external memory, its fifo is completed.

TxFWAR

: Tx DMA CONTROLLER FIFO WARNING

TxFWAR = 1, Tx DMA CONTROLLER has generated an interrupt, its fifo is 3/4 completed.

TxFOV

: Tx DMA CONTROLLER FIFO OVERLOAD

TxFOV = 1, Tx DMA CONTROLLER has generated an interrupt, it cannot transfer data from

Tx HDLC to external memory, its fifo is completed.

INTFWAR : INTERRUPT CONTROLLER FIFO WARNING

INTFWAR = 1, INTERRUPT CONTROLLER has generated an interrupt, its fifo is 3/4

completed.

INTFOV

: INTERRUPT CONTROLLER FIFO OVERLOAD

INTFOV = 1, INTERRUPT CONTROLLER has generated an interrupt, it cannot transfer

status from DMA and GCI controllers to external memory, its internal fifo is completed.

TIM

: TIMER

TIM = 1, the programmable timer has generated an interrupt.

VIII - INTERNAL REGISTERS (continued)

STLC5465B

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