STLC5465B datasheet(84/101 Pages) STMICROELECTRONICS

84 / 101 page

VIII.15 - Address Field Recognition Address Register - AFRAR (1C)H

bit15

bit8

bit7

bit 0

CH4

CH3

CH2

CH1

CHO

READ

AMM

After reset (0000)H

The write operation is lauched when AFRAR is written by the microprocessor.

AMM

: Access to Mask Memory.

AMM=1, Access to Address Field Recognition Mask Memory.

AMM=0, Access to Address Field Recognition Memory.

READ : READ ADDRESS FIELD RECOGNITION MEMORY

READ=1, READ AFR MEMORY.

READ=0, WRITE AFR MEMORY.

CH0/4 : These five bits define one of 32 channels in reception

VIII.16 - Address Field Recognition Data Register - AFRDR (1E)H

bit15

bit8

bit7

bit 0

AF15/

AFM15

AF14/

AFM14

AF13/

AFM13

AF12/

AFM12

AF11/

AFM11

AF10/

AFM10

AF9/

AFM9

AF8/

AFM8

AF7/

AFM7

AF6/

AFM6

AF5/

AFM5

AF4/

AFM4

AF3/

AFM3

AF2/

AFM2

AF1/

AFM1

AF0/

AFMO

After reset (0001)H

AF0/15 : ADDRESS FIELD BITS

AF0/7 ; First byte received; AF8/15: Second byte received.

These two bytes are stored into Address Field Recognition Memory when AFRAR is written by

the microprocessor.

AFM0/

15:

ADDRESS FIELD BIT MASK0/15 if AMM=1 (AMM bit of AFRAR)

AMF0/7. When AR10=1 (See HRCR) each bit of the first received byte is compared respectively

to AFx bit if AFMx=0. In case of mismatching, the received frame is ignored. If AFMx=1, no

comparison between AFx and the corresponding received bit.

AMF8/15. When AR20=1 (See HRCR) each bit of the second received byte is compared

respectively to AFy bit if AFMy=0. In case of mismatching, the received frame is ignored. If

AFMy=1, no comparison between AFy and the corresponding received bit.

These two bytes are stored into AddressField Recognition Mask Memory when AFRAR is written

by the microprocessor (AMM=1).

VIII.17 - Fill Character Register - FCR (20)H

bit15

bit8

bit7

bit 0

FC7

FC6

FC5

FC4

FC3

FC2

FC1

FC0

After reset (0000)H

FC0/7 : FILL CHARACTER (eight bits)

In Transparent Mode M1, twomessages are separatedby FILLCHARACTERS andthe detection

of one FILL CHARACTER marks the end of a message.

VIII.18 - GCI Channels Definition Register 0 - GCIR0 (22)H

The definitions of x and y indices are the same for GCIR0, GCIR1, GCIR2, GCIR3 :

-0

≤ x ≤ 7, 1 of 8 GCI CHANNELS belonging to the same multiplex TDM4 or TDM5

- y = 0, TDM4 is selected

- y = 1, TDM5 is selected.

VIII - INTERNAL REGISTERS (continued)

STLC5465B

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