STLC5465B datasheet(95/101 Pages) STMICROELECTRONICS

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IX.3 - Transmit Descriptor

This transmit descriptor is located in shared memory. The quantity of descriptors is limited by the memory

size only.

TDA+00

BINT

BOF

EOF

EOQ

Number of Bytes to be Transmitted (NBT)

TDA+02

Not used

CRC

PRI

TBA High (8 bits)

TDA+04

Transmit Buffer Address Low (16 bits)

TDA+06

Not used

NTDA High (8 bits)

TDA+08

Next Transmit Descriptor Address Low (16 bits)

TDA+10

CFT

ABT

UND

The 5 first words located in shared memory to TDA+00 from TDA+08 are written by the microprocessor

and read by the DMAC only. The 6th word located in shared memory in TDA+10 is written by the DMAC

only during the frame reception and read by the microprocessor.

NBT

: Number of Bytes to be transmitted (up to 4096).

TBA

: Transmit Buffer Address. LSB of TBA Low is at Zero mandatory.

TDA

: Transmit Descriptor Address.

NTDA : Next Transmit Descriptor Address. LSB of NTDA Low is at Zero mandatory.

IX.3.1 - Bits written by the Microprocessor only

BINT

: Interrupt at the end of the frame or when the buffer is become empty.

BINT = 1,

if EOF = 1 the DMAC generates an interrupt when the frame has been transmitted ;

if EOF = 0 the DMAC generates an interrupt when the buffer is become empty.

BINT = 0, the DMAC does not generate an interrupt during the transmission of the frame.

BOF

: Beginning Of Frame

BOF = 1,the transmit bufferassociated to this transmit descriptor contains the beginning of frame.

The DMA Controller will store automatically the current descriptor address in the Initialization

Block.

BOF = 0, the DMA Controller will not store the current descriptor address in the Initialization

Block.

EOF

: End Of Frame

EOF = 1,the transmit buffer associated to this transmit descriptor contains the end of frame.

EOF = 0,the transmit buffer associated to this transmit descriptor does not contain the end of

frame.

EOQ

: End Of Queue

EOQ = 1, the DMAC stops immediately its transmission, generates an interrupt (HDLC = 1 in

IR) and waits a command from the HTCR (HDLC Transmit Command Register).

EOQ = 0, the DMAC continues.

CRCC : CRC Corrupted

CRCC = 1,at the end of this frame the CRC will be corrupted by the Tx HDLC Controller.

PRI

: Priority Class 8 or 10

PRI = 1, if CSMA/CR is validated for this channel, the priority class is 8.

PRI = 0, if CSMA/CR is validated for this channel the priority class is 10.

(see Register CSMA)

IX - EXTERNAL REGISTERS (continued)

STLC5465B

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