STLC5465B datasheet(75/101 Pages) STMICROELECTRONICS

75 / 101 page

VIII - INTERNAL REGISTERS (continued)

TABLE: SWITCHING AT 16Kb/s WHEN ITS3 = 0

ITS 3 ITS 2 ITS 1 ITS 0

Upstream

Source: D channels of one of 16

GCI channels

Destination: two bits of one TDM

Downstream

Source: two bits of one TDM

Destination: D channels of one of 16

GCI channels

The contents of D channels of GCI

0 /3 of multiplex DIN4 are transferred

into the output timeslot of one TDM

defined by the destination register

(CMAR).

D channel of GCI 0 in bit 1/2

D channel of GCI 1 in bit 3/4

D channel of GCI 2 in bit 5/6

D channel of GCI 3 in bit 7/8

The contents of the input timeslot

(same number as the number of the

output timeslot) is transferred in D

channel of GCI 0/3 of multiplex

DOUT4

bit 1/2 in D channel of GCI 0

bit 3/4 in D channel of GCI 1

bit 5/6 in D channel of GCI 2

bit 7/8 in D channel of GCI 3

The contents of D channels of GCI

4/7 of multiplex DIN4 are transferred

into the output timeslot of one TDM

defined by the destination register

(CMAR).

D channel of GCI 4 in bit 1/2

D channel of GCI 5 in bit 3/4

D channel of GCI 6 in bit 5/6

D channel of GCI 7 in bit 7/8

The contents of the input timeslot

(same number as the number of the

output timeslot) is transferred in D

channel of GCI 4/7 of multiplex

DOUT4.

bit 1/2 in D channel of GCI 4

bit 3/4 in D channel of GCI 5

bit 5/6 in D channel of GCI 6

bit 7/8 in D channel of GCI 7

The contents of D channels of GCI 0

/3 of multiplex DIN5 are transferred

into the output timeslot of one TDM

defined by the destination register

(CMAR).

D channel of GCI 0 in bit 1/2

D channel of GCI 1 in bit 3/4

D channel of GCI 2 in bit 5/6

D channel of GCI 3 in bit 7/8

The contents of the input timeslot

(same number as the number of the

output timeslot) is transferred in D

channel of GCI 0/3 of multiplex

DOUT5.

bit 1/2 in D channel of GCI 0

bit 3/4 in D channel of GCI 1

bit 5/6 in D channel of GCI 2

bit 7/8 in D channel of GCI 3

The contents of D channels of GCI

4/7 of multiplex DIN5 are transferred

into the output timeslot of one TDM

defined by the destination register

(CMAR).

D channel of GCI 4 in bit 1/2

D channel of GCI 5 in bit 3/4

D channel of GCI 6 in bit 5/6

D channel of GCI 7 in bit 7/8

The contents of the input timeslot

(same number as the number of the

output timeslot) is transferred in D

channel of GCI 4/7 of multiplex

DOUT5.

bit 1/2 in D channel of GCI 4

bit 3/4 in D channel of GCI 5

bit 5/6 in D channel of GCI6

bit 7/8 in D channel of GCI 7

STLC5465B

75/101

STLC5465B Fiches technique(PDF) 75 Page - STMicroelectronics

STLC5465B Fiches technique(HTML) 75 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Fiches technique Télécharger

Lien URL