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STLC5465B Fiches technique(PDF) 49 Page - STMicroelectronics

No de pièce STLC5465B
Description  MULTI-HDLCWITH n x 64 SWITCHING MATRIX ASSOCIATED
PDF  101 Pages
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Fabricant  STMICROELECTRONICS [STMicroelectronics]
Site Internet  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STLC5465B Fiches technique(HTML) 49 Page - STMicroelectronics

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V1 - MEMORY TIMING
T
Total Re ad Cycle
Tu
HZ
HZ
HZ
HZ
E ach s ignal from the MHDLC is high
impe dance outside this time if MBL = 0
a
a
a
1/f
NDS fr o m
µP
(or e quivalent)
MASTERCLOCK
a pplied to XTAL1 P in
ADM0/10
NWE
NOE
DM0/15 from
DRAM Circuit
Note : Se e
MBL De finition
a
a
a
NRAS 0/3
Tv
NCAS 0/1
Tw
Tz
Tv/2
Ts
Tw + Tz /2
Th
Figure 38 : Dynamic Memory Read Signals from the
Multi-HDLC
VI.1 - Dynamic Memories
Symbol
Parameter
Min.
Typ.
Max.
Unit
T
Delay between Data Strobe from the mP and beginning of cycle
2/f
a
Delay between Masterclock and Edge of each signal delivered by the
MHDLC (30pF)
V DD =5V
V DD = 3.3V
20
30
40
ns
ns
Tw
Delay between NCAS Falling Edge and NCAS rising Edge
1/f
2/f
ns
Tz
Delay between NCAS Rising Edge and end of cycle
1/f
2/f
ns
Ts
Set-up Time Data /NCAS Rising Edge
20
ns
Th
Hold Time Data/NCAS Rising Edge
0
ns
STLC5465B
49/101



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