STLC5465B datasheet(4/101 Pages) STMICROELECTRONICS

4 / 101 page

TABLE OF CONTENTS (continued)

Page

V1 - MEMORY TIMING ... .. . . .... . . ... ....... . . ..... .. . . . . . . . . . 49

VI.1 - Dynamic Memories . . . . . . . . . . . . ...... ..... .... . . ... ...... 49

VI.2 - Static Memories . . . . . . . . . . . . .... .. . .... . . .. . . . . . . .... . . . 51

VII - MICROPROCESSOR TIMING ... .. . . .... . . ..... ..... . . ..... .. . . . 53

VII.1 - ST9 Family MOD0=1, MOD1=0, MOD2=0 . . . . . . . . . . . . . ..... ..... . . . 53

VII.2 - ST10/C16x mult. A/D, MOD0 = 1, MOD1 = 0, MOD2 = 1

. . . . . . . . . . . . . ..... 55

VII.3 - ST10/C16x demult. A/D, MOD0 = 1, MOD1 = 0, MOD2 = 1 . . . . ...... ... .... 57

VII.4 - 80C188 MOD0=1, MOD1=1, MOD2=0 . . . . . . . . . ...... .. . . .... . . ... 59

VII.5 - 80C186 MOD0=1, MOD1=1, MOD2=1 . . . . . . . . . ...... .. . . .... . . ... 61

VII.6 - 68000 MOD0=0, MOD1=0, MOD2=1

. . . . . . . . . ...... .. . . .... . . ... 63

VII.7 - 68020 MOD0=0, MOD1=0, MOD2=0 . . . . . . . .... . . ... .... . . . . . . . . . 65

VII.8 - Token Ring Timing . . . . . . . . . . . . ...... ..... .... . . ... ...... 67

VII.9 - Master Clock Timing . . . . . . . .... . . ....... .. . . ... ...... .... 67

VIII - INTERNAL REGISTERS

... .. . . .... . . ....... .. . . ... ...... .... 68

VIII.1 - Identification and Dynamic Command Register - IDCR (00)H .... .... .. . . . . . . 68

VIII.2 - General Configuration - GCR (02)H ... .. . .... ... ..... ..... . . .... 68

VIII.3 - Input Multiplex Configuration Register 0 - IMCR0 (04)H

.... .... .. . . . . . . .. 70

VIII.4 - Input Multiplex Configuration Register 1 - IMCR1 (06)H

.... .... .. . . . . . . .. 70

VIII.5 - Output Multiplex Configuration Register 0 - OMCR0 (08)H . . . ... ... . . . . . ... 71

VIII.6 - Output Multiplex Configuration Register 1 - OMCR1 (0A)H . . . ... ... . . . . . ... 71

VIII.7 - Switching Matrix Configuration Register - SMCR (0C)H

.... .... .. . . . . . . .. 71

VIII.8 - Connection Memory Data Register - CMDR (0E)H . . . ... ... . . . . . ....... 74

VIII.9 - Connection Memory Address Register - CMAR (10)H . . . ... ... . . . . . ..... 77

VIII.10 - Sequence Fault Counter Register - SFCR (12)H

. . . ... ... . . . . . ....... 79

VIII.11 - Time Slot Assigner Address Register - TAAR (14)H .... .... .. . . . . . . . . . . 79

VIII.12 - Time Slot Assigner Data Register - TADR (16)H

. . . ... ... . . . . . ....... 80

VIII.13 - HDLC Transmit Command Register - HTCR (18)H .... .... .. . . . . . . . . . . 81

VIII.14 - HDLC Receive Command Register - HRCR (1A)H .... .... .. . . . . . . . . . . 82

VIII.15 - Address Field Recognition Address Register - AFRAR (1C)H . . . ... ... . . . . .. 84

VIII.16 - Address Field Recognition Data Register - AFRDR (1E)H . . . ... ... . . . . . ... 84

VIII.17 - Fill Character Register - FCR (20)H . . . . ... . . . ... ..... ..... . . ... 84

VIII.18 - GCI Channels Definition Register 0 - GCIR0 (22)H .... .... .. . . . . . . . . . . 84

VIII.19 - GCI Channels Definition Register 1 - GCIR1 (24)H .... .... .. . . . . . . . . . . 85

VIII.20 - GCI Channels Definition Register 2 - GCIR2 (26)H .... .... .. . . . . . . . . . . 85

VIII.21 - GCI Channels Definition Register 3 - GCIR3 (28)H .... .... .. . . . . . . . . . . 85

VIII.22 - Transmit Command / Indicate Register - TCIR (2A)H . . . ... ... . . . . . ..... 86

Transmit Command/Indicate Register (after reading) . . . . ...... ... ...... 86

VIII.23 - Transmit Monitor Address Register - TMAR (2C)H

.... .... .. . . . . . . . . . . 87

Transmit Monitor Address Register (after reading) . . . . ...... ... ..... ... 87

VIII.24 - Transmit Monitor Data Register - TMDR (2E)H .... .... .. . . . . . . . . . . .. 88

VIII.25 - Transmit Monitor Interrupt Register - TMIR (30)H . . . ... ... . . . . . ....... 88

VIII.26 - Memory Interface Configuration Register - MICR (32)H .... .... .. . . . . . . .. 88

Memory

. . . . . . . . . . . . .... ..... . . ..... ....... .. ... . . 89

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