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STLC5465B Fiches technique(PDF) 65 Page - STMicroelectronics

No de pièce STLC5465B
Description  MULTI-HDLCWITH n x 64 SWITCHING MATRIX ASSOCIATED
PDF  101 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Fabricant  STMICROELECTRONICS [STMicroelectronics]
Site Internet  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STLC5465B Fiches technique(HTML) 65 Page - STMicroelectronics

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Symbol
Parameter
Min.
Typ.
Max.
Unit
t1
Delay NDTACK / NCS0/1 (if t3 > t1), (30pF)
Delay when immediate access
V DD =5V
V DD = 3.3V
0
0
98
108
ns
ns
t2
Hold Time Chip Select / NDS rising edge
0
ns
t3
Delay NDSACK1 / NDS Falling Edge (if t1> t3), (30pF)
Delay when immediate access
V DD =5V
V DD = 3.3V
0
0
98
108
ns
ns
t4
Delay NDSACK1 / NDS Rising Edge
V DD =5V
V DD = 3.3V
20
30
ns
ns
t5
Set-up Time Address and R/W/last NDS or NCS
0
ns
t6
Hold Time Address / NDS
0
ns
t7
Data valid before NDSACK1 falling edge (30pF)
0
15
ns
t8
Data High Impedance after NDS (30pF)
0
15
ns
NCS0/1
NDSACK0/
NDTACK
NDSACK1/
READY
NAS /
ALE
NDS /NRD
SIZE0/ NLDS
SIZE1/ NUDS
A0/23
R/W /NWR
D0/15
t1
t2
t5
t6
t4
t7
t3
t8
Figure 54 : 68020 Read Cycle
VII - MICROPROCESSOR TIMING (continued)
VII.7 - 68020 MOD0=0, MOD1=0, MOD2=0
STLC5465B
65/101



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