STLC5465B datasheet(80/101 Pages) STMICROELECTRONICS

80 / 101 page

HDI

: HDLC INIT

HDI = 1, TSA Memory, Tx HDLC, Tx DMA, Rx HDLC, Rx DMA and GCI controllers are reset

within 250ms. An automate writes data from Time slot Assigner Data Register (TADR) (except

CH0/4 bits) into each TSA Memory location. If the microprocessor reads Time slot Assigner

Memory after HDLC INIT, CH0/4 bits of Time slot Assigner Data Register are identical to TS0/4

bits of Time slot Assigner Address Register.

HDI = 0, Normal state.

N.B.

After software reset (bit 2 of IDCR Register) or pin reset the automate above-mentioned is

working. The automate is stopped when the microprocessor writes TAAR Register with HDI = 0.

VIII.12 - Time Slot Assigner Data Register - TADR (16)H

bit15

bit8

bit7

bit 0

V11

V10

CH4

CH3

CH2

CH1

CH0

After reset (0000)H

CH0/4 : CHANNEL0/4

These five bits define one of 32 channels associated to TIME SLOT defined by the previous

V1/8

: VALIDATION

The logical channel CHx is constituted by each subchannel 1 to 8 and validated by V1/8 bit at

1 respectively.

V1 to V8 at 0: the subchannels are ignored

V1 at 1: the first bit of the current time slot is taken into account in reception the first bit received

and in transmission the first bit transmitted.

V8 at 1: the last bit of the current time slot is taken into account in reception the last bit received

and in transmission the last bit transmitted in transmission.

: VALIDATION SUBCHANNEL

V 9 = 1, each V1/8 bit is taken into account once every 250ms.

In transmit direction, data is transmitted consecutively during the time slot of the current frame

and during the same time slot of the next frame.Id est.: the same data is transmitted in two

consecutive frames.

In receive direction, HDLC controller fetches data during the time slot of the current frame and

ignores data during the same time slot of the next frame.

V 9 = 0, each V1/8 bit is taken into account once every 125ms.

V10

: DIRECT MHDLC ACCESS

If V10 = 1, the Rx HDLC Controller receives data issued from DIN8 input during the current time

slot (bits validated by V1/8) and DOUT6 output transmits data issued from the Tx HDLC

Controller.

If V10 = 0, the Rx HDLC Controller receives data issued from the matrix output 7 during the

current time slot ; DOUT6 output delivers data issued from the matrix output 6 during the same

current time slot.

N.B : If D7 = 1, (see ”General Configuration Register GCR (02)H”) the Tx HDLC controller is

connected to matrix input 7 continuously so the HDLC frames can be sent to any DOUT (i.e.

DOUT0 to DOUT7).

V11

: VALIDATION of CB pin

This bit is not taken into account if CSMA = 1 (HDLC Transmit Command Register).

if CSMA = 0 :

V11 = 1, Contention Bus pin is validated and Echo pin (which is an input) is not taken into

account.

V11 = 0, Contention Bus pin is high impedance during the current time slot (This pin is an open

drain output).

VIII - INTERNAL REGISTERS (continued)

STLC5465B

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