PM0223 datasheet(48/110 Pages) STMICROELECTRONICS

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The STM32L0 Cortex-M0+ Instruction Set

PM0223

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DocID025763 Rev 1

3.4.3

LDR and STR, register offset

Load and Store with register offset.

Syntax

LDR Rt, [Rn, Rm]

LDR<B|H> Rt, [Rn, Rm]

LDR<SB|SH> Rt, [Rn, Rm]

STR Rt, [Rn, Rm]

STR<B|H> Rt, [Rn, Rm]

where:

Operation

LDR, LDRB, LDRH, LDRSB

and LDRSH load the register specified by Rt with either a

word, zero extended byte, zero extended halfword, sign extended byte or sign extended

halfword value from memory.

STR, STRB

and STRH store the word, least-significant byte or lower halfword contained in

the single register specified by Rt into memory.

The memory address to load from or store to is the sum of the values in the registers

specified by Rn and Rm.

Restrictions

In these instructions:

•

, Rn, and Rm must only specify R0-R7.

•

The computed memory address must be divisible by the number of bytes in the load or

store, see 3.3.4: Address alignment on page 42.

Condition flags

These instructions do not change the flags.

Examples

STR R0, [R5, R1]

; Store value of R0 into an address equal to

; sum of R5 and R1

LDRSH

R1, [R2, R3]

; Load a halfword from the memory address

; specified by (R2 + R3), sign extend to 32-bits

; and write to R1.

Is the register to load or store.

Is the register on which the memory address is based

s a register containing a value to be used as the offset

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