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PM0223 Fiches technique(PDF) 81 Page - STMicroelectronics |
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PM0223 Fiches technique(HTML) 81 Page - STMicroelectronics |
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81 / 110 page ![]() DocID025763 Rev 1 81/110 PM0223 STM32L0 Core Peripherals 108 4 STM32L0 Core Peripherals 4.1 About the STM32L0 core peripherals The address map of the Private Peripheral Bus (PPB) is: In register descriptions: the register type is described as follows: • the required privilege gives the privilege level required to access the register, as follows: Privileged Only privileged software can access the register. Unprivileged Both unprivileged and privileged software can access the register. Table 25. Core peripheral register regions Address Core peripheral Description 0xE000E008-0xE000E00F System Control Block Table 30 on page 88. 0xE000E010-0xE000E01F Reserved - 0xE000E010-0xE000E01F System timer Table 33 on page 95. 0xE000E100-0xE000E4EF Nested Vectored Interrupt Controller Table 26 on page 82. 0xE000ED00-0xE000ED3F System Control Block Table 30 on page 88. 0xE000ED90-0xE000EDB8 Memory Protection Unit(1) 1. Software can read the MPU Type Register at 0xE000ED90 to test for the presence of a Memory Protection Unit (MPU). Table 35 on page 99. 0xE000EF00-0xE000EF03 Nested Vectored Interrupt Controller Table 26 on page 82. RW Read and write. RO Read-only. WO Write-only. |
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