PM0223 datasheet(42/110 Pages) STMICROELECTRONICS

42 / 110 page

The STM32L0 Cortex-M0+ Instruction Set

PM0223

42/110

DocID025763 Rev 1

Figure 11. LSL #3

ROR

Rotate right by n bits moves the left-hand 32-nbits of the register Rm, to the right by n places,

into the right-hand 32-n bits of the result, and it moves the right-hand n bits of the register

into the left-hand n bits of the result. See Figure 12 on page 42.

When the instruction is RORS the carry flag is updated to the last bit rotation, bit[n-1], of the

Note:

If n is 32, then the value of the result is same as the value in Rm, and if the carry flag is

updated, it is updated to bit[31] of Rm.

If ROR with shift length, n, greater than 32 is the same as ROR with shift length n-32

Figure 12. ROR #3

3.3.4

Address alignment

An aligned access is an operation where a word-aligned address is used for a word, or

multiple word access, or where a halfword-aligned address is used for a halfword access.

Byte accesses are always aligned.

There is no support for unaligned accesses on the STM32L0 Cortex-M0+ processor. Any

attempt to perform an unaligned memory access operation results in a HardFault exception.

3.3.5

PC-relative expressions

A PC-relative expression or label is a symbol that represents the address of an instruction or

literal data. It is represented in the instruction as the PC value plus or minus a numeric

offset. The assembler calculates the required offset from the label and the address of the

current instruction. If the offset is too big, the assembler produces an error.

PM0223 Fiches technique(PDF) 42 Page - STMicroelectronics