PM0223 datasheet(93/110 Pages) STMICROELECTRONICS

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PM0223

STM32L0 Core Peripherals

108

4.3.7

Configuration and Control Register

The CCR is a read-only register and indicates some aspects of the behavior of the

STM32L0 Cortex-M0+ processor. See the register summary in Table 30 on page 88 for the

CCR attributes.

The bit assignments are

Bits 31:5

Reserved

Bit 4

SEVEONPEND Send Event on Pending bit

0 : Only enabled interrupts or events can wakeup the processor, disabled interrupts are

excluded.

1 = Enabled events and all interrupts, including disabled interrupts, can wakeup the

processor.

When an event or interrupt becomes pending, the event signal wakes up the processor from

WFE. If the processor is not waiting for an event, the event is registered and affects the next

WFE.

The processor also wakes up on execution of an SEV instruction or an external event.

Bit 3

Reserved, must be kept cleared

Bit 2

SLEEPDEEP

Controls whether the processor uses sleep or deep sleep as its low power mode:

0: Sleep

1: Deep sleep.

Bit 1

SLEEPONEXIT

Indicates sleep-on-exit when returning from Handler mode to Thread mode. Setting this bit to 1

enables an interrupt-driven application to avoid returning to an empty main application.

0: Do not sleep when returning to Thread mode.

1: Enter sleep, or deep sleep, on return from an ISR to Thread mode.

Bit 0

Reserved, must be kept cleared

Reserved

STK

ALIGN

BFHF

NMIGN

Reserved

DIV_0_

TRP

ALIGN_

TRP

Res.

USER

SET

MPEND

NON

BASE

THRD

ENA

Bits 31:10

Reserved, must be kept cleared

Bit 9

STKALIGN

Always reads as one, indicates 8-byte stack alignment on exception entry.

On exception entry, the processor uses bit[9] of the stacked PSR to indicate the stack

alignment. On return from the exception it uses this stacked bit to restore the correct stack

alignment.

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