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PM0223 Fiches technique(PDF) 28 Page - STMicroelectronics |
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PM0223 Fiches technique(HTML) 28 Page - STMicroelectronics |
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28 / 110 page ![]() The STM32L0 Cortex-M0+ Processor PM0223 28/110 DocID025763 Rev 1 2.3.3 Exception handlers The processor handles exceptions using: Interrupt Service Routines (ISRs) Interrupts IRQ0 to IRQ31 are the exceptions handled by ISRs Fault handler HardFault is the only exception handled by the fault handler. System handlers NMI, PendSV, SVCall SysTick, and HardFault are all system exceptions handled by system handlers. |
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