PM0223 datasheet(27/110 Pages) STMICROELECTRONICS

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PM0223

The STM32L0 Cortex-M0+ Processor

For an asynchronous exception, other than reset, the processor can execute additional

instructions between when the exception is triggered and when the processor enters the

exception handler.

Privileged software can disable the exceptions that Table 13 on page 27 shows as having

configurable priority, see 4.2.3: Interrupt Clear-enable Register on page 83.

For more information about HardFaults, see 2.4: Fault handling on page 33

SysTick

A SysTick exception is an exception the system timer generates when

it reaches zero. Software can also generate a SysTick exception. In

an OS environment, the processor can use this exception as system

tick.

Interrupt (IRQ)

An interrupt, or IRQ, is an exception signalled by a peripheral, or

generated by a software request. All interrupts are asynchronous to

instruction execution. In the system, peripherals use interrupts to

communicate with the processor.

Table 13. Properties of the different exception types

Exception

number(1)

1. To simplify the software layer, the CMSIS only uses IRQ numbers. It uses negative values for exceptions

other than interrupts. The IPSR returns the Exception number, see Interrupt Program Status Register on

page 16

IRQ

number(1)

Exception type

Priority

Vector

address(2)

2. See Figure 7.: Vector table on page 29 for more information.

Activation

Reset

-3, the highest

0x00000004

Asynchronous

2-14

NMI

-2

0x00000008

Asynchronous

-13

HardFault

-1

0x0000000C

Synchronous

4-10

Reserved

-5

SVCall

Configurable(3)

3. See 4.2.6: Interrupt Priority Registers on page 85

0x0000002C

Synchronous

12-13

Reserved

-2

PendSV

Configurable(3) 0x00000038

Asynchronous

-1

SysTick

Configurable(3) 0x0000003C

Asynchronous

Reserved

16 and above 0 and above Interrupt (IRQ)

Configurable(3)

0x00000040

and above

(4)

4. Increasing in steps of 4.

Asynchronous

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