PM0223 datasheet(66/110 Pages) STMICROELECTRONICS

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The STM32L0 Cortex-M0+ Instruction Set

PM0223

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DocID025763 Rev 1

3.6.1

B, BL, BX, and BLX

Branch instructions.

Syntax

B{cond} label

BL label

BX Rm

BLX Rm

where:

Operation

All these instructions cause a branch to the address indicated by label or contained in the

•

the BL and BLX instructions write the address of the next instruction to LR, the link

•

the BX and BLX instructions result in a HardFault exception if bit[0] of Rm is 0.

and BLX instructions also set bit[0] of the LR to 1. This ensures that the value is suitable

for use by a subsequent POP {PC} or BX instruction to perform a successful return branch.

Table 23 shows the ranges for the various branch instructions

Restrictions

In these instructions:

•

Do not use SP or PC in the BX or BLX instruction.

•

For BX and BLX, bit[0] of Rm must be 1 for correct execution. Bit[0] is used to update the

EPSR T-bit and is discarded from the target address.

Note:

cond

is the only conditional instruction on the STM32L0 Cortex-M0+ processor.

Cond

Is an optional condition code, see 3.3.6: Conditional execution on page 43.

label

Is a PC-relative expression. See 3.3.5: PC-relative expressions on page 42.

Is a register providing the address to branch to.

Table 23. Branch ranges

Instruction

Branch range

B label

−2 KB to +2 KB.

cond label

−256 bytes to +254 bytes.

BL label

−16 MB to +16 MB.

BX Rm

Any value in register.

BLX Rm

Any value in register.

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