PM0223 datasheet(99/110 Pages) STMICROELECTRONICS

99 / 110 page

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99/110

PM0223

STM32L0 Core Peripherals

108

Use the MPU registers to define the MPU regions and their attributes. Table 35 on page 99

shows the MPU registers

4.5.1

MPU Type Register

The MPU_TYPE register indicates whether the MPU is present, and if so, how many

regions it supports. See the register summary in Table 35 on page 99 for its attributes. The

bit assignments are:

Table 34. Memory attributes summary

Memory type

Shareability Other attributes

Description

Strongly- ordered -

All accesses to Strongly-ordered memory

occur in program order. All Strongly-ordered

regions are assumed to be shared.

Device

Shared

Memory-mapped peripherals that several

processors share.

Non-shared

Memory-mapped peripherals that only a

single processor uses.

Normal

Shared

Non-cacheable

Write-through

Cacheable Write-

back Cacheable

Normal memory that is shared between

several processors.

Non-shared

Non-cacheable

Write-through

Cacheable Write-

back Cacheable

Normal memory that only a single processor

uses.

Table 35. MPU registers summary

Address

Name

Type

Reset

value

Description

0xE000ED90

MPU_TYPE

0x00000000 or

0x00000800

(1)

1. Software can read the MPU Type Register to test for the precence of a Memory Protection Unit (MPU).

See MPU Type Register

4.5.1: MPU Type Register on

page 99.

0xE000ED94

MPU_CTRL

0x00000000

4.5.2: MPU Control Register on

page 100.

0xE000ED98

MPU_RNR

Unknown

4.5.3: MPU Region Number

0xE000ED9C

MPU_RBAR RW

Unknown

4.5.4: MPU Region Base Address

0xE000EDA0

MPU_RASR RW

Unknown

4.5.5: MPU Region Attribute and

Size Register on page 103.

Reserved

IREGION[7:0]

rrrr

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