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PM0223 Fiches technique(PDF) 38 Page - STMicroelectronics |
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PM0223 Fiches technique(HTML) 38 Page - STMicroelectronics |
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38 / 110 page ![]() The STM32L0 Cortex-M0+ Instruction Set PM0223 38/110 DocID025763 Rev 1 RSBS {Rd,} Rn, #0 Reverse Subtract N,Z,C,V 3.5.1 on page 54. SBCS {Rd,} Rn, Rm Subtract with Carry N,Z,C,V 3.5.1 on page 54. SEV - Send Event - 3.7.9 on page 77. STM Rn!, reglist Store Multiple registers, increment after - 3.4.5 on page 50. STR Rt, [Rn, <Rm|#imm>] Store Register as word - 3.4.2 on page 47. STRB Rt, [Rn, <Rm|#imm>] Store Register as byte - 3.4.2 on page 47. STRH Rt, [Rn, <Rm|#imm>] Store Register as halfword - 3.4.2 on page 47. SUB{S} {Rd,} Rn, <Rm|#imm> Subtract N,Z,C,V 3.5.1 on page 54. SVC #imm Supervisor Call - 3.7.10 on page 78. SXTB Rd, Rm Sign extend byte - 3.5.8 on page 63. SXTH Rd, Rm Sign extend halfword - 3.5.8 on page 63. TST Rn, Rm Logical AND based test N,Z 3.5.9 on page 64. UXTB Rd, Rm Zero extend a byte - 3.5.8 on page 63. UXTH Rd, Rm Zero extend a halfword - 3.5.8 on page 63. WFE - Wait For Event - 3.7.11 on page 79. WFI - Wait For Interrupt - 3.7.12 on page 80. Table 15. STM32L0 Cortex-M0+ instructions (continued) Mnemonic Operands Brief description Flags Section |
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