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PCF8811U/2DA/1 Fiches technique(PDF) 74 Page - NXP Semiconductors

No de pièce PCF8811U/2DA/1
Description  80 x 128 pixels matrix LCD driver
PDF  81 Pages
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Fabricant  NXP [NXP Semiconductors]
Site Internet  http://www.nxp.com
Logo NXP - NXP Semiconductors

PCF8811U/2DA/1 Fiches technique(HTML) 74 Page - NXP Semiconductors

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PCF8811_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 27 June 2008
74 of 81
NXP Semiconductors
PCF8811
80 x 128 pixels matrix LCD driver
with a logic 1 in order to program the corresponding OTP cell. If the shift register cell
contains a logic 0, then no action will take place when the programming voltages are
applied.
Once programmed, an OTP cell cannot be de-programmed. An already programmed cell,
i.e. an OTP cell containing a logic 1, must not be re-programmed.
During programming, a substantial current flows in the VLCDIN pad. For this reason it is
recommended to program only one OTP cell at a time. This is achieved by filling all but
one shift register cells with logic 0.
It should be noted that the programming specification refers to the voltages at the chip
pads, contact resistance must therefore be considered by the user.
An example sequence of commands and data for OTP programming is given in Table 40.
It is assumed that the PCF8811 has just been reset.
The order for programming cells is not significant. However, NXP Semiconductors
recommends that the seal bit is programmed last. Once this bit has been programmed
and the CALMM mode is exited, it is not possible to re-enter the CALMM mode.
[1]
X = value without meaning.
Table 40.
Sequence for filling the shift register; example 2[1]
Step Pad
Command byte
Action
EXT D/C R/W/WR DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
X
0
0
1
1
1
0
0
0
0
1
exit power-save
2
-
-
-
-
-
-
-
-
-
-
-
wait 5 ms for refresh to take effect
3
X
0
0
1
0
1
0
1
0
0
1
re-enter power-down (DON = 0)
4
X
0
0
1
0
0
0
0
0
1
0
enter CALMM mode
5
X
0
0
1
0
X
X
X
X
X
1
shift in data; MMVOPCAL[4] is first bit
6
X
0
0
1
0
X
X
X
X
X
1
MMVOPCAL[3]
7
X
0
0
1
0
X
X
X
X
X
1
MMVOPCAL[2]
9
X
0
0
1
0
X
X
X
X
X
0
MMVOPCAL[1]
10
X
0
0
1
0
X
X
X
X
X
0
MMVOPCAL[0]
11
X
0
0
1
0
X
X
X
X
X
0
MMTC[2]
12
X
0
0
1
0
X
X
X
X
X
1
MMTC[1]
13
X
0
0
1
0
X
X
X
X
X
0
MMTC[0]
14
X
0
0
1
1
X
X
X
X
X
0
seal bit
15
-
-
-
-
-
-
-
-
-
-
-
apply programming voltage at pads
VOTPPROG and VLCDIN; see Section 18.1.8
Repeat steps 5 to 14 for each bit which must be programmed to 1; exit CALMM mode
16
-
-
-
-
-
-
-
-
-
-
-
apply external reset



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