PCF8811USLASH2DASLASH1 datasheet(18/81 Pages) NXP

18 / 81 page

PCF8811_4

Product data sheet

Rev. 04 — 27 June 2008

18 of 81

NXP Semiconductors

PCF8811

80 x 128 pixels matrix LCD driver

7.1.19.3

DB3 and DB2 (I2C-bus interface)

DB3 and DB2 are respectively the SA1 and SA0 inputs when the I2C-bus interface is

selected and can be used so that up to four PCF8811s can be distinguished on one

I2C-bus interface.

7.1.20 OSC: oscillator

• When the on-chip oscillator is used this input must be connected to VDD1

• If an external clock signal is used, it is connected to this input

• If the oscillator and an external clock are both inhibited by connecting the OSC pad to

VSS1, the display is not clocked and may be left in a Direct Current (DC) state. To

avoid a DC on display, the chip should always be put into Power-down mode before

stopping the clock

7.1.21 RES: reset

This signal will reset the device and must be applied to properly initialize the chip. The

signal is active LOW.

7.2 Block diagram functions

See Figure 1 for the block diagram layout.

7.2.1 Oscillator

The on-chip oscillator provides the clock signal for the display system. No external

components are required, and the OSC input must be connected to VDD1. An external

clock signal, if used, is connected to this input.

7.2.2 Address counter

The address counter assigns addresses to the display data RAM for writing. The X

address X[6:0] and the Y address Y[3:0] are set separately.

7.2.3 Display data RAM

The PCF8811 contains an 80

× 128 bit static RAM which stores the display data.

• The RAM is divided into 10 banks of 128 bytes (10

× 8 × 128 bit)

• The icon row (when enabled) is always row 79 and located in bank 9

• During RAM access, data is transferred to the RAM via the parallel interface, serial

interface or I2C-bus interface

• There is a direct correspondence between the X address and the column output

number

7.2.4 Timing generator

The timing generator produces the various signals required to drive the internal circuitry.

Internal chip operation is not affected by operations on the data bus.

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