PCF8811USLASH2DASLASH1 datasheet(26/81 Pages) NXP

26 / 81 page

PCF8811_4

Product data sheet

Rev. 04 — 27 June 2008

26 of 81

NXP Semiconductors

PCF8811

80 x 128 pixels matrix LCD driver

The parallel interface timing diagram for the 6800 series is given in Section 16.1,

Figure 39 and Figure 40. The timing diagrams differ because in Figure 39 the clock is

connected to the enable (E) input. In Figure 40 the clock is connected to the chip enable

input (SCE) and the enable input (E) is tied HIGH.

10. Serial interfacing (SPI and serial interface)

Communication with the microcontroller can also occur via a clock-synchronized Serial

Peripheral Interface (SPI). It is possible to select between either a 3-line (SPI or serial

interface) or a 4-line serial peripheral interface. Selection is achieved via PS[2:0];

see Section 7.1.12).

10.1 Serial peripheral interface lines

The serial peripheral interface is a 3-line or 4-line interface for communication between

the microcontroller and the LCD driver chip. The 3 lines are:

• SCE (chip enable)

• SCLK (serial clock)

• SDATA (serial data)

For the 4-line serial peripheral interface a separate D/C line is added.

The PCF8811 is connected to the serial data I/O (SDA) of the microcontroller by

connecting the two pads SDATA (data input) and SDO (data output) together.

10.1.1 Write mode

The display data/command indication may be controlled either via software or the D/C

select pad. When the D/C pad is used, display data is transmitted when D/C is HIGH, and

command data is transmitted when D/CisLOW;see Figure 15 and Figure 16. When pad

D/C is not used, the display data length instruction is used to indicate that a speciﬁc

number of display data bytes (1 to 255) are to be transmitted; see Figure 17. The next

byte after the display data string is handled as an instruction command.

When the 3-line SPI interface is used, the display data/command is controlled by software.

If SCE is pulled HIGH during a serial display data stream, the interrupted byte is invalid

data but all previously transmitted data is valid. The next byte received will be handled as

an instruction command; see Figure 18.

Table 8.

6800 series parallel interface functions

D/C

R/W/WR

Operation

command data write

read status register

display data write

none

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