PCF8811USLASH2DASLASH1 datasheet(62/81 Pages) NXP

62 / 81 page

PCF8811_4

Product data sheet

Rev. 04 — 27 June 2008

62 of 81

NXP Semiconductors

PCF8811

80 x 128 pixels matrix LCD driver

[1]

All speciﬁed timings are based on 20 % and 80 % of VDD.

[2]

tH5 is the time from the previous SCLK rising edge (irrespective of the state of SCE) to the falling edge of

SCE.

[3]

SDO disable time for SPI 3-line or 4-line.

[4]

SDO disable time for 3-line serial interface.

[5]

Maximum values are for fSCLK = 9 MHz. Series resistance includes ITO track + connector resistance +

printed-circuit board.

SCE hold time

SDO disable time

[4] 25

100

capacitive load for SDO

[5] -30

series resistance for SDO

[5] -

500

Ω

Table 33.

Serial interface timing characteristics[1] …continued

VDD1 = 1.8 V to 3.3 V; VSS = 0 V; VLCD ≤ 9 V; Tamb = −40 °C to +85 °C; unless otherwise speciﬁed;

see Figure 41, Figure 42, Figure 43 and Figure 44.

Symbol

Parameter

Min

Max

Unit

Fig 41. 3-line serial interface timing

mgw757

tH1

tPWH1

tPWL1

tS1

tS2

tH2

tH5

Tcyc

(tH5)

tPWH2

SCE

SCLK

SDATA

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