PCF8811USLASH2DASLASH1 datasheet(34/81 Pages) NXP

34 / 81 page

PCF8811_4

Product data sheet

Rev. 04 — 27 June 2008

34 of 81

NXP Semiconductors

PCF8811

80 x 128 pixels matrix LCD driver

As no device is allowed to acknowledge the master code, the master code is followed by a

not-acknowledge (A). After this A bit, and the SCLH line pulled up to a HIGH level, the

active master switches to Hs-mode and enables at tH the current-source pull-up circuit for

the SCLH signal; see Figure 30.

The active master will then send a repeated START condition (Sr) followed by a 7-bit slave

address (SLA) with a R/W bit, and receives an acknowledge bit (A) from the selected

slave.

After each acknowledge bit (A) or not-acknowledge bit (A) the active master disables its

current source pull-up circuit. The active master re-enables its current source again when

all devices have been released and the SCLH signal reaches a HIGH level. The rising of

the SCLH signal is done by a pull-up resistor and therefore is slower, the last part of the

SCLH rise time is speeded up because the current source is enabled. Data transfer only

switches back to F/S-mode after a STOP condition (P).

A write sequence after the Hs-mode is selected is shown in Figure 31. The sequence is

initiated with a START condition (S) from the I2C-bus master which is followed by the slave

address. All slaves with the corresponding address acknowledge in parallel, the remainder

will ignore the I2C-bus transfer.

Fig 30. Data transfer timing format in F/S-mode and Hs-mode

msc618

8-bit master code 0000 1xxx

F/S-mode

Hs-mode

If P then

F/S-mode

If Sr (dotted lines)

then Hs-mode

2 to 5

SDAH

SCLH

SDAH

SCLH

tFS

Sr P

n + (8-bit data

A/A)

7-bit SLA

R/W

= Master current source pull-up

= Resistor pull-up

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