ORSPI4 datasheet(27/263 Pages) LATTICE

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ORCA ORSPI4 Data Sheet

SPI4 Transmit Path Functional Description

This section describes the transmit section of the SPI4 interface. The ORSPI4 device contains two identical, yet

independent Transmit SPI4 compliant interfaces within the FPSC. The description provided within this section is

applicable to both Transmit SPI4 interfaces.

The Transmit SPI4 interface supports the following features:

• Independent TX interface that is not tied to associated Receive SPI4 interface

• 10 Gbit/s data throughput

• 4 dual-port memories used to provide 256 Bytes of buffering for up to 32 ports. If support for more than 32 ports

is required, the dual-port memories can be used, or they can be used for clock crossing purposes while data is

buffered with external memory.

• Simple FIFO-like interface from FPGA to SPI4 TX embedded core block.

• Calendar Control Logic, including the Transmit Calendar, Shadow Calendar and support for up to 256 ports (the

maximum allowable number of SPI4 ports).

• Mixed data width aggregation modes at the user Transmit interface. 32, 64, and 128-bit modes are supported.

• Programmable calendar table, supporting all calendar conﬁguration parameters as speciﬁed in the SPI4 stan-

dard.

• Feedback to FPGA of currently serviced SPI4 port.

The Transmit SPI4 logic enables users to write port data from a variety of interfaces and associated clock domains

using Dual Port RAMs (DPRAM) for temporary storage and clock domain crossing. Data is written into the DPRAM

banks from the FPGA and read according to a pre-conﬁgured transmit calendar sequence. Data is formatted into

the SPI4 format and transmitted to the physical links as LVDS signals, as speciﬁed by OIF-SPI4-02.0.

In addition to the transmit data path, out-of-band status information is received on the Transmit Status lines. This

information is used, along with preconﬁgured Calendar sequence information, to schedule the servicing of SPI4

port for data transmission. The status information is also passed back to the FPGA logic. There are also several

other features incorporated into the embedded core such as parallel loopback and SPI4 loopback to assist in

debugging and statistic gathering.

The major blocks associated with the ORSPI4 transmitter are:

• Four Transmit DPRAM Banks

• Address Map and Arbiter (AMA)

• Transmit Calendar Control Logic

– Port Write Sequencer Logic (PWS)

• SPI4 Logic - Data

– SPI4 Transmit Data Logic (TDP)

– SPI4 Transmit I/O Interface (TDO)

• SPI4 Transmit Status Logic (TSP)

– SPI4 Transmit Status Interface (TSI)

– SPI4 Transmit Status Protocol (TSP)

These blocks will be described in detail in the following sections. The ORSPI4 Transmit functional block diagram is

shown in Figure 10.

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