ORSPI4 datasheet(47/263 Pages) LATTICE

47 / 263 page

Lattice Semiconductor

ORCA ORSPI4 Data Sheet

Figure 17. Port 1 and 2 Disable

TX DPRAM

The TX DPRAMs consist of four 256 x 160 memories, that can each be partitioned into a maximum of 8 equally

sized virtual partitions, providing a maximum of 32 virtual FIFO partitions. By providing a simple FIFO-like interface

to the FPGA, the FPGA can access FIFO partitions by asserting a 3-bit address ﬁeld. Internal logic maintains both

write and read pointers and provides a programmable FIFO_FULL ﬂag to the FPGA logic in order to prevent over-

ﬂow conditions.

Data may be written into the DPRAMs using either multiple 32-, or 64-bit interfaces, or alternatively using a single

128-bit interface. The sideband control bus is present for each individual interface. The DPRAM partition depths are

a function of the interface width used, as well as the number of conﬁgured partitions. Table 7 shows the depth of

virtual partitions for data and sideband control information based upon the write interface width and the number of

partitions.

Table 7. Memory Size for Each Aggregation Mode and Partitioning

Write Interface Mode

# of Conﬁgured

Virtual FIFO

Partitions

DATA FIFO Depth

(in Bytes)

Control FIFO Depth

(in Bytes)

32-bit

512

256

512

128

256

64-bit

14K

512

256

512

128

128-bit

18K

24K

512

256

302

SPIB_TX32_PORT_ID[7:0]

SPIB_TX32_LINK_DIS_3

SPIB_TX32_LINK_DIS_2

SPIB_TX32_LINK_DIS_1

SPIB_TX32_LINK_DIS_0

SPIB_TX32_CLK_0

ORSPI4 Fiches technique(PDF) 47 Page - Lattice Semiconductor

ORSPI4 Fiches technique(HTML) 47 Page - Lattice Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Fiches technique Télécharger

Lien URL