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ORCA ORSPI4 Data Sheet

rate of the data lane. The MUX/DEMUX converts the data rate and bus width so the interface to the FPGA core can

run at 1/4th this intermediate frequency, giving a range of 25.0 to 92.5 MHz for the data rates into and out of the

FPGA logic.

Multi-Channel Alignment FIFOs

In the ORSPI4 SERDES block, the four incoming data channels can be independent of each other or can be syn-

chronized in several ways. Two channels within a SERDES block can be aligned together; channels A and B and/or

channels C and D. Finally, four channels in a SERDES block can be aligned together to form a communication

channel with a bandwidth of 10 Gbits/s. Individual channels within an alignment group can be disabled (i.e., pow-

ered down) without disrupting other channels.

XAUI and Fibre Channel Link State Machines

Two separate link state machines are included in the architecture. A XAUI-based link state machine is included in

the embedded core to implement the IEEE 802.3ae standard. A separate state machine for Fibre Channel is also

implemented.

FPGA/Embedded Core Interface

In 8b/10b mode, the FPGA logic will receive/transmit 32-bits of data (up to 92.5 MHz) and four K_CTRL bits from/to

the embedded core. There are 4 data streams in each direction plus additional timing, status and control signals.

Data sent to the FPGA can be aligned using comma (/K/) characters or /A/ character as speciﬁed either by Fibre

Channel or by IEEE 802.3ae for XAUI based interfaces. The alignment character is made available to the FPGA

along with the data. The special characters K28.1, K28.5 and K28.7 are treated as valid comma characters by the

SERDES.

If the receive channel alignment FIFOs are bypassed, then each channel will provide its own receive clock in addi-

tion to data and comma character detect signals. If the 8b/10b decoders are bypassed, then 40-bit data streams

are passed to the FPGA logic. No channel alignment can be done in 8b/10b bypass mode.

SERDES Features

• Four channels of 0.6-3.7G SERDES with 8b/10b encoding/decoding are supported. The SERDES quad is IEEE

P802.3ae/D4.01 XAUI based and also supports the FC (ANSI X3.230:1994) link synchronization state machine

speciﬁcation.

• The high-speed SERDES are programmable and support serial data rates including 622 Mbits/s, 1.0 Gbits/s,

1.25 Gbits/s, 2.5 Gbits/s, 3.125 Gbits/s, and 3.7 Gbits/s. Operation has been demonstrated on design tolerance

devices at 3.7 Gbits/s across 26 in. of FR-4 backplane and at 3.2 Gbits/s across 40 in. of FR-4 backplane across

temperature and voltage speciﬁcations.

• Asynchronous operation per receive channel, with the receiver frequency tolerance based on one reference

clock per four channels (separate PLL per channel).

• Ability to select full-rate or half-rate operation per transmit or receive channel by setting the appropriate control

registers.

• Programmable one-half amplitude transmit mode for reduced power in chip-to-chip application.

• Transmit preemphasis (programmable) for improved receive data eye opening.

• 32-bit (8b/10b) or 40-bit (raw data) parallel internal bus for data processing in FPGA logic.

• Provides a 10 Gbits/s backplane interface to a switch fabric using four 2.5 Gbit/s links. Also supports port cards

at 2.5 Gbit/s.

• 3.125 Gbits/s SERDES compliant with XAUI serial data speciﬁcation for 10 Gigabit Ethernet applications.

• Most XAUI features for 10 Gigabit Ethernet are embedded including the required link state machine.

• Compliant to Fibre Channel physical layer speciﬁcation.

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