ORSPI4 datasheet(73/263 Pages) LATTICE

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ORCA ORSPI4 Data Sheet

Table 13. SPIA Core Receive FPGA Interface in 64-Bit Mode

DPRAM

FPGA Interface I/Os

Direction

From/To

Description

SPIA_RX64_ADDR_0[2:0]

FPGA

→ Core FIFO read address.

SPIA_RX64_DATA_0[63:0]

Core

→FPGA FIFO read data.

SPIA_RX64_BE_0[7:0]

Core

→FPGA Byte enables

Bit 7 - Byte enable for SPIA_RX64_DATA_0[63:56]

Bit 6 - Byte enable for SPIA_RX64_DATA_0[55:48]

Bit 5 - Byte enable for SPIA_RX64_DATA_0[47:40]

Bit 4 - Byte enable for SPIA_RX64_DATA_0[39:32]

Bit 3 - Byte enable for SPIA_RX64_DATA_0[31:24]

Bit 2 - Byte enable for SPIA_RX64_DATA_0[23:16]

Bit 1 - Byte enable for SPIA_RX64_DATA_0[15:8]

Bit 0 - Byte enable for SPIA_RX64_DATA_0[7:0]

SPIA_RX64_CTL_0

Core

→FPGA Port ID indicator. A ‘1’ indicates that the SPIA_RX64_DATA_0 bus contains

the port ID.

SPIA_RX64_SOP_0

Core

→FPGA Start of Packet Indicator. A ‘1’ indicates start of packet.

SPIA_RX64_EOP_0

Core

→FPGA End of Packet Indicator. A ‘1’ indicates end of packet.

SPIA_RX64_ERR_0

Core

→FPGA Error. A ‘1’ indicates an error in the current word.

SPIA_RX64_FIFO_EMPTY_0 Core

→FPGA FIFO Empty ﬂag. Depends on the RX_DPRAM_EMPTY_TYPE_SELA[0]

software register bit in address 0x30920. When this bit is set to ‘0’, (default)

the empty ﬂag indicates truly empty.

When this bit is set to ‘1’, the empty ﬂag indicates that the FIFO is 1/4 full -1.

ASTOP_ON_EOP0

FPGA

→ Core Timing control for handling end of packet.

SPIA_RX64_CLK_0

FPGA

→ Core FIFO read clock.

SPIA_RX64_RD_0

FPGA

→ Core FIFO read enable.

SPIA_RX64_ADDR_1[2:0]

FPGA

→ Core FIFO read address.

SPIA_RX64_DATA_1[63:0]

Core

→FPGA FIFO read data.

SPIA_RX64_BE_1[7:0]

Core

→FPGA Byte enables

Bit 7 - Byte enable for SPIA_RX64_DATA_1[63:56]

Bit 6 - Byte enable for SPIA_RX64_DATA_1[55:48]

Bit 5 - Byte enable for SPIA_RX64_DATA_1[47:40]

Bit 4 - Byte enable for SPIA_RX64_DATA_1[39:32]

Bit 3 - Byte enable for SPIA_RX64_DATA_1[31:24]

Bit 2 - Byte enable for SPIA_RX64_DATA_1[23:16]

Bit 1 - Byte enable for SPIA_RX64_DATA_1[15:8]

Bit 0 - Byte enable for SPIA_RX64_DATA_1[7:0]

SPIA_RX64_CTL_1

Core

→FPGA Port ID indicator. A ‘1’ indicates that the SPIA_RX64_DATA_1 bus contains

the port ID.

SPIA_RX64_SOP_1

Core

→FPGA Start of Packet Indicator. A ‘1’ indicates start of packet.

SPIA_RX64_EOP_1

Core

→FPGA End of Packet Indicator. A ‘1’ indicates end of packet.

SPIA_RX64_ERR_1

Core

→FPGA Error. A ‘1’ indicates an error in the current word.

SPIA_RX64_FIFO_EMPTY_1 Core

→FPGA FIFO Empty ﬂag. Depends on the RX_DPRAM_EMPTY_TYPE_SELA[0]

software register bit in address 0x30920. When this bit is set to ‘0’, (default)

the empty ﬂag indicates truly empty.

When this bit is set to ‘1’, the empty ﬂag indicates that the FIFO is 1/4 full -1.

ASTOP_ON_EOP1

FPGA

→ Core Timing control for handling end of packet.

SPIA_RX64_CLK_1

FPGA

→ Core FIFO read clock.

SPIA_RX64_RD_1

FPGA

→ Core FIFO read enable.

Note: For SPIB replace A with B

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