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ORCA ORSPI4 Data Sheet

Receive Address Mapper

This control block decodes the port address received from the SPI4 RX interface to determine the physical memory

address (to access the DPRAM memories) for that port address. Each port address must be mapped to one of the

virtual FIFOs in the DPRAMs. Each virtual FIFO can be used to buffer data for a single port. Since there is a total

of four DPRAMs, eight virtual FIFOs in each DPRAM provides 32 per-port buffers. The number of per-port buffers

varies according to the operating mode. For example, in 32-bit mode, a total of 32 per-port buffers is possible. In

64-bit mode, a total of 16 per-port buffers is provided. In 128-bit mode, a total of eight per-port buffers is provided.

To decode the physical memory information, this block accesses a user-conﬁgured Port Descriptor Memory (PDM)

which is simply a look-up-table. The PDM is an embedded memory within the ORSPI4 core. There is one each for

SPIA and SPIB cores. Since 256 ports can be supported by the device, the PDM has 256 locations. The user

indexes this memory using the 8-bit SPI4 Port ID as the software write address into the embedded memory space

31000 - 310FF. For example, a software write into address 31000 conﬁgures the PDM for port ID 0. The software

procedure to conﬁgure the PDM is described below:

• User has to select the PDM by writing a ‘1’ into bit 3 of address 30917 (SPIA) or 30A17 (SPIB).

• Subsequent writes to addresses 31000-310FF correspond to entries 0x00-0xFF in the PDM. These may be writ-

ten in any order.

• Upon completion of the PDM conﬁguration, the PDM select bit (bit 3 of address 30917 or 30A17) must be set to

‘0’.

• The contents of the PDM may also be read back. This is done by ﬁrst selecting the PDM memory by writing a ‘1’

to bit 3 of address 30917 or 30A17. Reads are then done from addresses 31000-310FF. Upon completion of the

reads, the PDM select bit is set to ‘0’.

To allocate a buffer space to a port, the user has to choose one of the four DPRAM banks (BANK_ID ﬁeld in the

PDM) and a virtual FIFO (PARTITION_ID) within the chosen DPRAM bank. Each location in the PDM contains the

ﬁelds described below for each port address.

128-bit data width, partition size 1

128-bit data width, partition size 2

128-bit data width, partition size 4

128-bit data width, partition size 8

DPRAM 3

(Register Bits 6:7) = 00

32-bit data width, partition size 1

32-bit data width, partition size 2

32-bit data width, partition size 4

32-bit data width, partition size 8

64-bit data width, partition size 1

64-bit data width, partition size 2

64-bit data width, partition size 4

64-bit data width, partition size 8

128-bit data width, partition size 1

128-bit data width, partition size 2

128-bit data width, partition size 4

128-bit data width, partition size 8

DPRAM Aggregation

Mode

Address 30907 (SPIA),

30A07 (SPIB)

Virtual FIFO Partition Size

Address 30906 (SPIA),

30A06 (SPIB)

Conﬁguration

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